Found 409 Articles for Microcontroller

The memory and the peripheral chips present today are very fast for a 8085 processor working at 3 MHz of frequency. So we do not need wait states. If we use 8085AH-2 which works at 5 MHz frequency, there we need to insert one wait state, between T2 and T3.To D-type positive edge-triggered flip flops are used by the circuit with an active low Reset inputs. At the beginning of T1, the Address Latch Enable goes very high and causes Q1 to go high. Since Q1 and D2 are connected, D2 remains very high throughout T1. The positive edge of ... Read More

The 8085AH-2 always works with a clock period of 200nS. We start the calculations by assuming that the valid address, and IO/M* signals are sent by the 8085AH-2 time 0 nS. After that the, Arithmetic Logical Unit moves to state 0 at 50 nS (tAL), and RD* gets activated at 115 nS (tAC).Earliest data output time considering tAcc: Address ranging from A13 to A18 is received by 27128 from 8085 processor by means of the octal line driver 74LS244 at 12 ns of time. Address ranging from A7 to A0 is received by the 27128 from 8085 processor by means of 74LS373. So ... Read More

Let’s perform the memory compatibility check with respect to tAD, tLDR, and tRD parameters.Compatibility with respect to tAD: The time interval between valid address on the addresses ranging from A15 to A0 and valid data on the addresses ranges from AD7 to AD0. For 8085AH the T state working is 320 nS, but it consists of a maximum of 575 nS. But here the valid data is available for 365 nS. So the speed of the memory is compatible, with an excess time margin of 575 nS - 365 nS = 210 nS.Compatibility with respect to tLDR: The time interval between the edge of ... Read More

The 8085AH activates the RD* Signal at 270 nS. This signal moves to OE* pin of 27128 through the octal line driver 74LS241 delayed by 12nS. Hence the signal OE* signal is received by 27128 at the end of time 282 nS. Hence the data can only come out from the pins ranging from D7 to D0 of 27128 by 282 nS + tOE = 282 nS + 75 nS + 357 nS.From the discussion done previously it should be crystal clear that the earliest data output time should be 357 nS, by considering all the three parameters tACC, tCE, and ... Read More

The 74138 receives the addresses ranging from A15 to A14 from 8085 Processor by means of the octal line driver 74LS244 which delays 12-nS. Simultaneously IO/M* signal is received from 8085 Processor via 74LS244. After that the CS* signal gets receive by the 27128 from 74LS138 which is 3 to 8 decoder, with a delay of 22 Nano seconds. Hence 27128 receives the CS* signal at the end of 34 nS. Hence the data only comes out from the pins ranging from D7 to D0 of 27128 by 34 nS + tCE = 34 nS + 200 nS = 234 nS. Delays involved in accessing 27128 EPROM in ALS kit.Bus timing characteristics of MR machine cycle

27128 receives the Address A13-8 by 27128 from 8085AH by means of the octal line driver 74LS244, which has a propagation delay of 12 nS. Address ranging from A7-0 is received by 27128 from 8085AH by means of 74LS373 octal latch, which consists of a propagation delay of 30 nS. Thus, address ranging from A13-0 is received by 27128 at the end of 30 nS. So the data only comes out on D7-0 pins of 27128 by 30 nS + tAcc = 30 nS + 200 nS = 230 nS.  Delays involved in accessing 27128 EPROM in ALS kit. Bus timing characteristics of MR machine cycle

At the end of the state T2 in a machine cycle, 8085 processor senses the Ready input pin. If it is logic 0, 8085 processors enter the Twait state, else it enters to the T3 state. The Ready input is permanently fixed to logic 1. The memory chips and the Input Output ports in the system same speed with 8085. Else appropriate number of wait states should be generated by the external circuit. In fact, in the ALS kit the Ready pin should be fixed to logic 1As an example, we check up if the 27128A-20 16K×8 EPROM chip are used ... Read More

So far we have come across OF, MR, MW, IOR, and IOW machine cycles. The other possible machine cycles in 8085 are BI (bus idle) and INA (interrupt acknowledge) machine cycles. Now the differences between some of the machine cycles are presented in the following tables.Difference between OF and MR1. Number of T states in case for OF is 4, Number of T states in case for MR is 32. In case of OF address can be sent out from PC. Whereas in case of MR it can be sent from BC, PC, DE, HL etc.3. In case of OF, ... Read More

The three clock cycles at the last stages in the IN 35H instruction is an example of machine cycle for IOR. The Waveforms for the IOR machine cycle are shown in the figure below.The point to be noted that in an IOR machine cycle, Wand Z has identical has port address of 8 bit. The value of 16 bit in the register pair WZ are sent out as the address in an Input Output Read machine cycle. Also the point to be noted that in an IOR machine cycle, only the data is received by the accumulator from the addressed ... Read More

The last three clock cycles in the OUT 25H instruction is an example for IOW machine cycle. Waveforms for IOW machine cycle are shown in the figure below: The point to be noted that in an IOW machine cycle, Wand Z registers have identical 8-bit port address. There is also a definite advantage because of address duplication on the addresses ranging from A15-8 and AD7-0 when we are using 8755 (2K × 8 EPROM and two 8-bit ports) and 8155 which is a combination of 256 × 8 RAM, 3 Input Output ports, and 14-bit timer. We can form a 8085-based ... Read More