The 74138 receives the addresses ranging from A15 to A14 from 8085 Processor by means of the octal line driver 74LS244 which delays 12-nS. Simultaneously IO/M* signal is received from 8085 Processor via 74LS244. After that the CS* signal gets receive by the 27128 from 74LS138 which is 3 to 8 decoder, with a delay of 22 Nano seconds. Hence 27128 receives the CS* signal at the end of 34 nS. Hence the data only comes out from the pins ranging from D7 to D0 of 27128 by 34 nS + tCE = 34 nS + 200 nS = 234 nS.
Delays involved in accessing 27128 EPROM in ALS kit.
Bus timing characteristics of MR machine cycle