Assessing compatibility of 27128-20 with 8085AH-2 in 8085 Microprocessor

The 8085AH-2 always works with a clock period of 200nS. We start the calculations by assuming that the valid address, and IO/M* signals are sent by the 8085AH-2 time 0 nS. After that the, Arithmetic Logical Unit moves to state 0 at 50 nS (t_AL), and RD* gets activated at 115 nS (t_AC).

Earliest data output time considering t_Acc: Address ranging from A_{13 to A18} is received by 27128 from 8085 processor by means of the octal line driver 74LS244 at 12 ns of time. Address ranging from A_{7 to A0 is} received by the 27128 from 8085 processor by means of 74LS373. So the, 27128 receives the address A_13-0 at the end of 30 nS. So the data only comes out on D_7-0 pins of 27128 by 30 nS + t_Acc = 30 nS + 200 nS = 230 nS.

Earliest data output time considering t_CE: The addresses are received by 74138 from the addresses A_15-14 from 8085 processor by the octal line driver.

Earliest data output time considering t_OE: The 8085AH-2 activates RD* signal at 115 nS of time. This signal moves to OE* pin of 27128.