The 8085AH-2 always works with a clock period of 200nS. We start the calculations by assuming that the valid address, and IO/M* signals are sent by the 8085AH-2 time 0 nS. After that the, Arithmetic Logical Unit moves to state 0 at 50 nS (tAL), and RD* gets activated at 115 nS (tAC).
Earliest data output time considering tAcc: Address ranging from A13 to A18 is received by 27128 from 8085 processor by means of the octal line driver 74LS244 at 12 ns of time. Address ranging from A7 to A0 is received by the 27128 from 8085 processor by means of 74LS373. So the, 27128 receives the address A13-0 at the end of 30 nS. So the data only comes out on D7-0 pins of 27128 by 30 nS + tAcc = 30 nS + 200 nS = 230 nS.
Earliest data output time considering tCE: The addresses are received by 74138 from the addresses A15-14 from 8085 processor by the octal line driver.
Earliest data output time considering tOE: The 8085AH-2 activates RD* signal at 115 nS of time. This signal moves to OE* pin of 27128.