The 8085AH activates the RD* Signal at 270 nS. This signal moves to OE* pin of 27128 through the octal line driver 74LS241 delayed by 12nS. Hence the signal OE* signal is received by 27128 at the end of time 282 nS. Hence the data can only come out from the pins ranging from D7 to D0 of 27128 by 282 nS + tOE = 282 nS + 75 nS + 357 nS.
From the discussion done previously it should be crystal clear that the earliest data output time should be 357 nS, by considering all the three parameters tACC, tCE, and tOE. Moreover, tAcc can be 200nS + (357 nS – 230 nS) is equal to 327 nS, without affecting any time at which the data comes out from the memory chip. Similarly, tCE can be big as 200 nS + (357 nS – 234 nS) which is equal to 323 nS, without affecting any time at which the data releases from the memory chip.
From 27128 data is received by the octal bus transceiver 74LS245 with a delay of 8 ns. Therefore, the valid data gets received by 8085AH at 357 nS + 8 nS is equal to 365 nS.