Shelving is an advanced issue mode, which is employed to eliminate issue blockages due to dependencies. Shelving makes use of dedicated instruction buffers, called shelving buffers, in front of each EU. The design space of shelving is shown in the figure. It consists of the following four main components such ... Read More

VLIW ArchitectureVLIW represents a Very long instruction word. It is an instruction set architecture constructed to take complete benefit of instruction-level parallelism (ILP) for upgraded performance.Central processing unit processors enable programs to designate instructions to execute in order only whereas a VLIW processor enables programs to explicitly determine instructions to ... Read More

The PentiumPro is the flagship of Intel’s x86 line of processors. The Pentium Pro processor performs a dynamic implementation microarchitecture such as a specific set of multiple branch prediction, data flow analysis, and speculative implementation. The Pentium Pro processor has a decoupled, 12- phases, super pipelined implementation, trading less work ... Read More

The PowerPC 620 is the highest performance model of the PowerPC line. It is the first chip for the application server and high-tech office product line inside the PowerPC family. It uses a high-execution microarchitecture with several advanced superscalar features to exploit instruction-level parallelism.The PowerPC 620 has six EUs capable ... Read More

The MIPS R10000 is the latest architecture of the R line of processors. It implements the MIPS IV ISA (Instruction Set Architecture), which is a superset of the MIPS III, supported for instance by the R8000. At a planned clock rate of 200 MHz, this four-way superscalar processor has a ... Read More

ROB stands for reorder buffer. The ROB was first expressed by Smith and Pleszkun in 1988. They conceived the ROB to solve the precise interrupt problem. The ROB is a round buffer with head and tail pointers.The head pointer denotes the area of the next complimentary entry. Instructions are written ... Read More

Load and store instructions involve actions affecting both the processor and the memory. While executing, both load and stores must first wait for their addresses to be computed by an ALU or address unit. Then, loads can access the data cache to fetch the requested memory data which is then ... Read More

Sequential consistency of instruction execution associates with two techniques such as first to the order in which instructions are finished and second to the order in which memory is created because of the load and store instruction or memory references of other instructions as shown in the figure.The term processor ... Read More

The design space of register renaming resembles that of shelving. As shown in the figure, it consists of the following main components such as the scope of register renaming, the layout of rename buffers, the operand fetch policy, and the number of renames per cycle.Scope of Register RenamingMost first-generation superscalar ... Read More

When instructions are executed in parallel, they will be completed in out-of-program order. Here, it does not matter whether instructions are issued or dispatched in order or out-of-order, or whether shelving is used or not. The point is that unequal execution times force instructions to finish out-of-order, even if they ... Read More