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What is R10000?
The MIPS R10000 is the latest architecture of the R line of processors. It implements the MIPS IV ISA (Instruction Set Architecture), which is a superset of the MIPS III, supported for instance by the R8000. At a planned clock rate of 200 MHz, this four-way superscalar processor has a peak performance of 800 MIPS.
Features of R10000
The R10000 has the following main features which are as follows −
It is a four-way superscalar processor with a maximum dispatch rate of five.
It uses pre-decoding.
It has three group reservation stations.
Operands are fetched about instruction dispatch.
Renaming is implemented using a merged architectural and rename register file.
Sequential consistency is preserved using a ROB.
R10000 execution core consists of the following main units: decode/issue unit, FX and FP register mapping tables, three group reservation stations, merged FX and FP register files, seven EUs, and the ROB. The EUs are as follows: three FX units and four FP units. The FX units are the IU1, IU2 (Integer Unit), and the AU (Address Unit). Both IU1 and IU2 can perform a wide range of simple arithmetic and logical instruction.
In addition, IU2 can carry out integer multiply and divide operations. The address unit (AU) is an address adder for generating addresses. The available FP units are dedicated to FP additions (FADD), multiplication (FMUL), division (FDIV), and square root calculations (FSQRT).
The R10000 has a short five-page pipeline for FX operations, consisting of the Fetch, Decode, Dispatch, Execute, and Writeback cycles. The R10000 employs pre-decoding to shorten the critical decode/issue/rename path. In each cycle, four predecoded instructions are fetched from the I-cache (Fetch cycle). Subsequently, all four instructions are decoded, issued, and renamed in the next cycle (Decode cycle). Both decoding and issue are carried out in program order.
Decoded register numbers of issued instructions are renamed. Each mapping table has 32 entries and enough read and write ports to rename up to four instructions of the same type in each cycle.
The FX mapping table provides 12 reads and 4 write ports while the FP table has 16 reads and 4 write ports. Thus, FX instructions may have up to three and FP instructions at most four operands.
Destination and source register numbers are renamed quite differently. During renaming, each destination register is allocated a new physical register out of the 64 physical registers available in each of the merged FX and FP register files, provided that a free register is at hand.
In addition, each table is updated with the newly established mappings of up to four destination registers. Source registers are renamed simply by reading the actual physical register numbers, which are allocated to the architectural registers concerned from the related mapping table.
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