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What is ROB?
ROB stands for reorder buffer. The ROB was first expressed by Smith and Pleszkun in 1988. They conceived the ROB to solve the precise interrupt problem. The ROB is a round buffer with head and tail pointers.
The head pointer denotes the area of the next complimentary entry. Instructions are written into the ROB in strict program order. As instructions are issued, a new entry is designated to each in sequence.
An instruction is enabled to retire only if it has been completed and all earlier instructions are previously retired. This approach provides that instructions retire strictly in order. Sequential consistency is continued in that only retiring instructions are allowed to complete, that is, to refresh the program state by writing their result into the referenced architectural register (s) or memory.
A ROB also naturally assists in interrupt handling. Interrupts generated in connection with instruction execution can easily be made precise by obtaining interrupt requests only when the associated instruction becomes the next to retire.
ROBs are more versatile. The design space of ROBs is shown in the figure. In the simplest layout, a ROB provides just reordering.
In the next layout, a ROB is used for both reordering and renaming. In this case, each ROB entry has to provide space to hold the result of the corresponding instructions as well. In the third alternative, the ROB is used for shelving as well and is frequently referred to as the DRIS (Deferred Scheduling, Register Renaming Instruction Shelf).
In this case, the ROB also has to provide space for shelving, which means either space for the source register numbers or space for source operands, depending on the operand fetch policy.
The ROB size determines the multiple entries in the ROB. This parameter limits the number of activities that is, issued but not finished, instructions in a processor. The total number of shelves and the number of reorder buffer entries must be in balance.
The reorder buffers hold all pending, that is, not yet completed, instructions. Some of the pending instructions are waiting in the shelving buffers for their operands and dispatch. Others are in the process of execution. Therefore, we expect more reorder buffer entries than shelves in recent superscalar processors.
The retire rate defines the maximum number of instructions that can be completed by the ROB in each cycle. This value indicates the maximum throughput of the processor.
The processor can be considered as consisting of several sequentially linked subsystems, which are decoupled from each other by some kind of buffers. These subsystems are fetched, issue, dispatch, execute and retire.
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