The PowerPC 620 is the highest performance model of the PowerPC line. It is the first chip for the application server and high-tech office product line inside the PowerPC family. It uses a high-execution microarchitecture with several advanced superscalar features to exploit instruction-level parallelism.
The PowerPC 620 has six EUs capable of parallel operations. These units are as follows − a branch processing unit (BPU), two simple integer units (IU1 and IU2) performing one-cycle integer and logical operations, a single multi-cycle integer unit (MIU) performing mainly integer multiplications and division, a load/store unit (L/SU) and an FP unit (FPU).
The main features of the PowerPC 620 are as follows −
It is a four-way superscalar processor.
It employs individual reservation stations.
Renaming is implemented by separate architectural and rename register files.
Sequential consistency is preserved using a reorder buffer.
The PowerPC 620 employs individual reservation stations with two to four buffers. Two buffers are available in the integer and FP units, whereas the L/SU has three entries and the BPU four.
Renaming is carried out using separate architectural registers and rename registers. The PowerPC 620 utilizes eight FX and eight FP rename registers. Sequential consistency of the execution is maintained by 16-entry reorder buffers (ROB).
Operand availability in the rename registers is managed through the use of scoreboarding. Thus, as part of the issue process, the scoreboard bits of the renamed destination registers are reset. This indicates for all subsequent instructions that the related register value is still unavailable.
Operands are fetched during the issue. Thus, at the same time as instructions are being forwarded to the reservation stations, up to eight FX register numbers and three FP register numbers are passed to the appropriate register files. Corresponding rename and architectural registers are simultaneously searched for the requested register values.
If a required source operand is found in one of the rename registers and its value is valid, that is, available, the content of that register is forwarded into the appropriate field of the corresponding reservation station.
If the required register value is contained in the rename register, but its value is not accessible, a tag, which is the rename register identifier, is stored in the reservation station in place of the operand value.
Operand fetching from the rename registers is quite a complex task. Each rename register has four fields. These are the rename valid bit, the register number to which this rename register is allocated, the result value if available, and the result valid bit.
Fetching operands from the rename registers requires an associative search since the contents of the register number fields must be searched for matching source register numbers..
Furthermore, since subsequent instructions may use the same destination register, the architectural register can have multiple renames. During an associative search, the latest rename is to be accessed. Thus, accessing operands from the rename registers requires an associative search for the youngest renamed value of the requested source register.