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What is design space of delayed branching?
There are two possible ways of extending the basic concepts such as increasing the multiplicity of delay slots or introduce annulment of instruction in the delay slot. Most architecture provides one delay slot only. Few architectures are offering multiple delay slots, such as the MIPS-X.
The other possibility to fill more delay slots is to introduce annulment (also called nullification or squashing). The basic idea is to introduce options in using delay slots, which can permit more delay slots to be filled than in the case of the basic scheme. Four different types of annulment can be introduced. The four variants are distinguished by whether the delay slot is annulled or not for the taken and not-taken paths.
The variants are −
No annulment (Branch-with-execute)
Annual delay slot if the branch is not taken (Branch-or-skip)
Annual delay slot if the branch is taken (Branch-with-skip)
Annual always
The first variant is the designated branch-with-execute. It is equivalent to the basic delay branching scheme. The branch-or-skip scheme allows a delay slot to be annulled if the branch is not taken. It can be used for backward conditional branches, to move instruction from within the loop body into the delay slot.
The branch-with-skip variant permits the annulment of the delay slot if the branch is taken. This is useful for forward conditional branches, to relocate an instruction from the sequential path into a delay slot. Finally, the annual always scheme allows optional delayed branching to be introduced.
Architecture with annulment usually provides two of the above-mentioned possibility on a select basis as shown in the table. It is worth noting that in most main-line RISC architectures, which emerged in the second half of the 1980s, annulment has been introduced in some form to increase performance. Examples are the HP PA, the SPARC, and the MC 88100 architecture.
Possible annulment options provided by architectures with delayed branching
| Branch-with-execute | Branch-or-skip | Branch-with-skip | Annual always | Multiplicity of delay slot | ||
|---|---|---|---|---|---|---|
| Annulment of an instruction in a delay slot | ||||||
| IBM 801 (1978) | X | X | 1 | |||
| MIPS-X (1986) | X | X | 2 | |||
| HP PA (1986) | X | X1 | X2 | 1 | ||
| SPARC (1987) | X | X | 1 | |||
| MC 88100 (1988) | X | X | 1 | |||
| i860 (1988) | X | X | 1 | |||
- Backward Branches
- Forward branches
Most architectures that provide an extended scheme for delayed branching offer, in addition to the basic scheme (Branch-with-execute), the Branch-or-skip option. This is usually done by providing for each branch instruction, two different forms, one with no annulment and the other with a certain type of annulment.
These forms are usually distinguished in assembly language syntax by different mnemonics (like BNZ and BNZX in the MIPS-X), or by an optional suffix (such as n in the MC 88100 family).
It also offers the possibility of annulling the instruction in the delay slot for unconditional branches, for instance in the HP PA, SPARC, and MC 88100.
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