Superscalar instruction issue is the most sensitive task of superscalar operation. The issue policy determines how dependencies are managed during the issue process. The issue rate defines the maximum number of instructions a superscalar processor can issue in each cycle.
The design space of issue policy is complex. As shown in the figure, it consists of four major aspects. The first two define how false data and unresolved control dependencies are coped with during instruction issues. In both cases, the design options are to prevent them during instruction issues by using register renaming and speculative branch processing.
The third condition decides whether issue blockages will be extremely decreased by the technique of shelving and the final condition defines how to deal with issue blockages.
False Data Dependencies − The design space of issue policy such as the first condition decides how the processor copes with false data dependencies. False dependencies appear between the instructions to be issued and those in execution or among the instructions to be issued.
The principle of eliminating false data dependencies between registered data by renaming is elementary. When encountering a WAW or WAR dependency, the processor renames the destination register creating the dependency.
Control Dependencies − The second condition of issue policies decides how to deal with control dependencies. A conditional control transfer instruction makes serious issues during pipelined instruction processing.
Shelving or indirect issue − The third condition of issue policy concerns the use of shelving, an adequate technique to avoid issue blockages. The blocking issue is also called a direct issue. It is a rigid approach associated with dependencies. This scheme controls the decoded instructions to be issued for dependencies as displayed in the figure. When dependencies appear, the instruction issue is blocked.
Checking for dependencies takes place in a so-called issue window. The issue window is n instructions wide, where n is the issue rate. The issue window includes the last n entries of the instruction buffer. In the absence of dependencies, all instructions in the window are issued directly to the execution units.
The shelved issue is also called an indirect issue. It decouples instructions issues and dependency checking. This technique assumes that special instruction buffers are generally defined as reservation stations, and are supported in front of the execution units. With shelving, instructions are issued first to the shelving buffers with basically no requirement for dependency checks as displayed in the figure.
When shelving is used, no dependency checks are executed between the instructions in the issue window and those in execution. This type of dependency checking is delayed to the next step of processing known as dispatching.
Handling issue blockages − The last aspect of the design space of instruction issue declares how occurring issue blockages are handled. Instruction issues can be blocked in both cases, with or without shelving. As long as shelving is not used, any dependencies encountered in the issue window immediately block the issue of instructions. In contrast, when shelving is used, issue blockages due to data and unresolved control dependencies are avoided.