Software-based approaches define a good and competitive concession because they need virtually negligible hardware support and they can lead to a similarly limited number of invalidation failures as the hardware-based protocols. All the software-based protocols depend on compiler support. The design space of software-based protocols is shown in the figure.The ... Read More

The Scalable Coherent Interface (IEEE P1596) is establishing an interface standard for very high-implementation multiprocessors. It can be providing a cache-coherent-memory model extensible to systems with up to 64K nodes. This Scalable Coherent Interface (SCI) will amount to a peak bandwidth per node of 1 GigaByte/second.The major purpose of the ... Read More

Directory schemes selectively send consistency commands only to those caches where the valid copy of the shared data block is stored. A directory entry must be associated with each data block. The directory entry consists of a set of pointers to the caches holding a valid copy of the block. ... Read More

Snoopy cache protocols are very popular in shared bus multiprocessors due to their relative simplicity. They have both write-update and write-invalidate policy versions. Write-invalidate snoopy cache protocols resemble this protocol in many ways and therefore are also easy to understand after studying a write-update protocol.The definition of transmission routes of ... Read More

Hardware-based protocols support general solutions to the issues of cache coherence without any condition on the cachability of data. Hardware-based protocols can be classified as follows −Memory update policy − There are two types of memory update policy are used in multiprocessors. The write-through policy maintains consistency between the main ... Read More

In multistage network-based shared memory systems, thousands of processors can try for a similar memory location. This location is called a hotspot and can significantly enlarge latency in the interconnection network. When two processors attempt to access the same memory location, their message will conflict in one of the switches ... Read More

The limited bandwidth of the single shared bus represents a major limitation in building scalable multiprocessors. There are several ways to increase the bandwidth of the interconnection network. A natural idea is to multiply the number of buses, like the processors and memory units. Four different ways have been proposed ... Read More

Arbiter logic plays a crucial act in the implementation of pended and split-transaction buses. These are the so-called 1 of N arbiters since they grant the requested resource only to one of the requesters. The design space of arbiter logic is very rich. There are two ways to organize the ... Read More

One of the most famous interconnection networks is the single shared bus. Firstly, its organization is simply a generalization and extension of the buses employed in uniprocessors and some additional ones to solve the contention on the bus when several processors simultaneously want to use the shared bus. These lines ... Read More

COMA stands for Cache-only memory access machines. A COMA machine includes several processing nodes connected by an interconnection network. Each processing node has a high-implementation processor, a cache, and an allocation of the global shared memory.COMA machines try to avoid the problems of static memory allocation of NUMA and CC-NUMA ... Read More