Classic mask-programmed ROM chips are joined circuits that physically encode the information to be saved, and therefore it is inaccessible to modify their contents after fabrication. Several methods of non-volatile solid-state memory allow some degree of modification −Programmable read-only memory (PROM) − It is a one-time programmable ROM (OTP) and ... Read More

Convex was the first device produce to commercialize a CC-NUMA machine, known as the SPP1000. SPP represents a Scalable Parallel Processor. The goals of the SPP Exemplar series are to make a family of high-implementation computers where the multiple processors can simply range from 10 to 1000 and the peak ... Read More

The Wisconsin multicube architecture employs row and column buses constructing a two-dimensional grid structure as shown in the figure. The three-dimensional generalization will appear in a cube structure.It can describe the cache coherence protocol of the Wisconsin multicube architecture, the following definitions must be given −Possible state of blocks in ... Read More

Software-based approaches define a good and competitive concession because they need virtually negligible hardware support and they can lead to a similarly limited number of invalidation failures as the hardware-based protocols. All the software-based protocols depend on compiler support. The design space of software-based protocols is shown in the figure.The ... Read More

The Scalable Coherent Interface (IEEE P1596) is establishing an interface standard for very high-implementation multiprocessors. It can be providing a cache-coherent-memory model extensible to systems with up to 64K nodes. This Scalable Coherent Interface (SCI) will amount to a peak bandwidth per node of 1 GigaByte/second.The major purpose of the ... Read More

Directory schemes selectively send consistency commands only to those caches where the valid copy of the shared data block is stored. A directory entry must be associated with each data block. The directory entry consists of a set of pointers to the caches holding a valid copy of the block. ... Read More

Snoopy cache protocols are very popular in shared bus multiprocessors due to their relative simplicity. They have both write-update and write-invalidate policy versions. Write-invalidate snoopy cache protocols resemble this protocol in many ways and therefore are also easy to understand after studying a write-update protocol.The definition of transmission routes of ... Read More

Hardware-based protocols support general solutions to the issues of cache coherence without any condition on the cachability of data. Hardware-based protocols can be classified as follows −Memory update policy − There are two types of memory update policy are used in multiprocessors. The write-through policy maintains consistency between the main ... Read More

In multistage network-based shared memory systems, thousands of processors can try for a similar memory location. This location is called a hotspot and can significantly enlarge latency in the interconnection network. When two processors attempt to access the same memory location, their message will conflict in one of the switches ... Read More

The limited bandwidth of the single shared bus represents a major limitation in building scalable multiprocessors. There are several ways to increase the bandwidth of the interconnection network. A natural idea is to multiply the number of buses, like the processors and memory units. Four different ways have been proposed ... Read More