Arbiter logic plays a crucial act in the implementation of pended and split-transaction buses. These are the so-called 1 of N arbiters since they grant the requested resource only to one of the requesters. The design space of arbiter logic is very rich. There are two ways to organize the ... Read More

One of the most famous interconnection networks is the single shared bus. Firstly, its organization is simply a generalization and extension of the buses employed in uniprocessors and some additional ones to solve the contention on the bus when several processors simultaneously want to use the shared bus. These lines ... Read More

COMA stands for Cache-only memory access machines. A COMA machine includes several processing nodes connected by an interconnection network. Each processing node has a high-implementation processor, a cache, and an allocation of the global shared memory.COMA machines try to avoid the problems of static memory allocation of NUMA and CC-NUMA ... Read More

CC-NUMA stands for Cache-coherent non-uniform memory access machines. A CC-NUMA machine includes several processing nodes linked through a high-bandwidth low-latency interconnection network. Each processing node includes a high-implementation processor, the related cache, and an allocation of the global shared memory.Cache coherence is preserved by a directory-based, write-invalidate cache coherence protocol. ... Read More

Cray T3D is the most recent NUMA machine that was designed to provide a highly scalable parallel supercomputer that can incorporate both the shared memory and the message-passing programming paradigms. As in other NUMA machines, the shared memory is distributed among the processing elements to avoid the memory access bottleneck ... Read More

Hector is a hierarchical NUMA machine consisting of stations connected by a hierarchy of ring networks. Stations are symmetric multiprocessors where the processing modules are linked by an individual bus. Nodes comprise three main units − a processor/cache unit, a memory unit, and the station bus interface which connects the ... Read More

NUMA represents Non-uniform Memory Access. NUMA is a multiprocessor model in which each processor is connected with the dedicated memory. Non-uniform memory access (NUMA) machines were intended to prevent the memory access bottleneck of UMA machines. The logically shared memory is physically assigned among the processing nodes of NUMA machines, ... Read More

UMA represents Uniform memory access. It is a shared memory architecture used in parallel computers. All the processors in the UMA model share the physical memory uniformly. In UMA architecture, access time to a memory location is autonomous of which processor creates the request or which memory chip includes the ... Read More

In adaptive routing, intermediate nodes can take the actual network conditions, including the presence of deterioration or bottlenecks, into account and decide accordingly which neighbor the message should be transmitted. Adaptive routing scheme can be either profitable or misrouting according to the selection of the output channel. In profitable routing, ... Read More

In deterministic routing, the path is fully determined by the source and destination nodes. Intermediate nodes are unable to direct messages even in the case of network congestion.Deterministic routing can be further classified according to the node position where the deterministic path is selected. In source routing, it is the ... Read More