Shared Memory MIMD Architectures is known as Multiprocessor. It can consider a set of processors and a set of memory modules. Any processor can directly access any memory module through an interconnection network as displayed in the figure. The set of memory modules represent a global address space that is ... Read More

Distributed memory MIMD Architecture is known as Multicomputer. It can replicate the processor/memory pairs and link them through an interconnection network. The processor/memory pair is known as the processing element (PE) and PEs work more or less separated from each other.Whenever interaction between them is possible through message passing one ... Read More

Guarded execution is a means to eliminate; at least partly, conditional branches. The idea is to introduce conditional operate instructions into the architecture and use them to replace conditional branches. Conditional operate instructions are called guarded instructions. A guarded instruction consists of two parts, a conditional part called the guard ... Read More

Multiway branching is another possibility for reducing branch penalties. With multiway branching, both the sequential and the taken paths of an unresolved conditional branch are pursued, as shown in the figure. The multiway branching requires multiple program counters (PCs) referred to as IFA1 and IFA2 in the figure.Once the specified ... Read More

Branch processing comprises basic tasks, such as instruction fetch, decode and BTA calculation, and possibly additional dedicated tasks to speed up branch processing. These dedicated tasks may be early branch detection, branch prediction, or an advanced scheme for accessing target paths.Usually, the dedicated tasks are executed using dedicated hardware, like ... Read More

This is the latest scheme introduced to access branch targets, employed in a few recently announced processors such as the Am29000 superscalar, K5, and UltraSparc. Here, the basic idea is to append, for each line in the I-cache, a successor index that points to the next line to be fetched ... Read More

This scheme is only used occasionally, in cases when the taken penalty would be intolerable high due to a longer than I-cache latency. The basic idea of the BTIC scheme is to provide a small extra cache that delivers, for taken or predicted taken branches, the branch target instruction or ... Read More

This scheme employs a more cache, known as the branch target address cache (BTAC), for speeding up access to branch targets as shown in the figure. The BTAC includes a group of currently used branch addresses and branch target addresses and is accessed relatively.When the actual instruction fetch address is ... Read More

This scheme is the common approach to accessing branch targets. First, the branch target address (BTA) is evaluated either by the pipeline or by a dedicated adder. Thus, the matching branch target instruction (BTI) is fetched. In current processors, this defines access to the I-cache, whereas in initial pipelined processors ... Read More

There are two basic tasks to be implemented the discard the results of the speculative execution and resume execution of the alternative, that is, the true path as shown in the figure.When there is higher than one pending conditional branch, the corresponding alternative path should be chosen and followed. In ... Read More