Switching is the actual mechanism by which a message is removed from the input buffer and placed in the output buffer. The switching technique applied has an over-whelming effect on message latency and hence the choice of switching method is crucial in designing any distributed memory computer. The design space ... Read More

In a static network, the connection between input and output nodes is fixed and cannot be modified. Static interconnection network cannot be reconfigured. Examples of this network are linear array, ring, chordal ring, tree, star, fat tree, mesh, tours, systolic arrays, and hypercube. The design space for static interconnection topologies ... Read More

Direct Interconnection networks are used to connect different processing elements or different process memory. Interconnection networks are also known as multi-stage interconnection networks (or MINs), are high-speed computer networks.Characteristics of Direct Interconnection NetworkTopology − It denotes how the nodes of a network are organized.Network Diameter − It is the minimum ... Read More

Shared Memory MIMD Architectures is known as Multiprocessor. It can consider a set of processors and a set of memory modules. Any processor can directly access any memory module through an interconnection network as displayed in the figure. The set of memory modules represent a global address space that is ... Read More

Distributed memory MIMD Architecture is known as Multicomputer. It can replicate the processor/memory pairs and link them through an interconnection network. The processor/memory pair is known as the processing element (PE) and PEs work more or less separated from each other.Whenever interaction between them is possible through message passing one ... Read More

Guarded execution is a means to eliminate; at least partly, conditional branches. The idea is to introduce conditional operate instructions into the architecture and use them to replace conditional branches. Conditional operate instructions are called guarded instructions. A guarded instruction consists of two parts, a conditional part called the guard ... Read More

Multiway branching is another possibility for reducing branch penalties. With multiway branching, both the sequential and the taken paths of an unresolved conditional branch are pursued, as shown in the figure. The multiway branching requires multiple program counters (PCs) referred to as IFA1 and IFA2 in the figure.Once the specified ... Read More

Branch processing comprises basic tasks, such as instruction fetch, decode and BTA calculation, and possibly additional dedicated tasks to speed up branch processing. These dedicated tasks may be early branch detection, branch prediction, or an advanced scheme for accessing target paths.Usually, the dedicated tasks are executed using dedicated hardware, like ... Read More

This is the latest scheme introduced to access branch targets, employed in a few recently announced processors such as the Am29000 superscalar, K5, and UltraSparc. Here, the basic idea is to append, for each line in the I-cache, a successor index that points to the next line to be fetched ... Read More

This scheme is only used occasionally, in cases when the taken penalty would be intolerable high due to a longer than I-cache latency. The basic idea of the BTIC scheme is to provide a small extra cache that delivers, for taken or predicted taken branches, the branch target instruction or ... Read More