Working of the 8257 DMA controller

Initially the processor programs 8257. Here the processor behaves as the master and 8257 here works in the slave mode. The channel of the program is obtained by writing to the Address Register from the starting address of memory for transferring Data, and writing to the Counter Register where the number of bytes to be transferred is by using the Direct Memory Access Scheme. The number of bytes of information which is specified by the Least Significant 14 bits. Whereas The Most Significant 2 bits indicate what type of data transfer is to occur. After that the processor writes to the control port which intel calls as special mode register. It specifies the DMA channels which are enabled, distinguished they are fixed or rotating. When an I/O port needs DMA service, activation of the DRQ input of a channel occurs, where in turns 8257 activates the HRQ. The output of HRQ is again connected to the HOLD input of 8085 where via DMA request the HOLD input of 8085 is activated. Then 8085 completes the current machine cycle which again goes to the HOLD state. Here the address pins HOLD state the address pins, RD*, WR*, and IO/M* pins are tristate. Here 8085 is disconnected from the rest of the system. It declares that HLDA output is activated by the HOLD state.

The 8057, which was previously a slave to the 8085, by receiving commands from 8085, it becomes the master of the computer.

DMA data transfers are classified as follows −

  • Single-byte transfer
  • Short-burst mode
  • Long burst mode
  • Single-byte transfer − A DMA request for each byte of DMA data transfer used to generate by some I/O ports like Intel 8272. The following steps are performed for each byte of data transfer.
    • Intel 8272 activates the DRQ input of 8257.

    • Intel 8257 activates the HOLD input of 8085, by activating HRQ output.

    • Intel 8085 enters the HOLD state, suspends program in execution, and activates the HLDA output.

    • Intel 8257 activates the DACK* output.

    • Intel 8257 generates the required control signals to perform data transfer of a byte. The AR is incremented and CR is decremented.

    • Intel 8272 deactivates the DRQ request.

    • Intel 8257 deactivates the HOLD input of 8085, by deactivating the HRQ output.

    • Intel 8085 comes out of the HOLD state and deactivates the HLDA output.

    • Intel 8085 resumes suspended program for some time.

    • Intel 8272 reactivates the DRQ and the sequence repeated till TC is reached.

  • Short-burst mode − Till several bytes are transferred, some I/O ports like Intel 8275 generate a DRQ and keep it active. Depending upon how 8275 is programmed, the DRQ input of the 8257 is kept active, for up to eight DACK* activations. This results in 8 bytes of DMA data transfer. For a quite some time, the DRQ output remains inactive. The HRQ output of 8257 becomes inactive resulting in 8085 coming out of HOLD state and getting into active state, during this period. Then according to the above mentioned sequence, it is repeated till all the bytes are transferred and the TC output is activated. This kind of a data transfer is known as Short-burst mode transfer, as the DRQ input remains active till a small block of data is transferred. This scheme is used with moderately fast peripherals.

  • Long-burst mode − Only after all the bytes are transferred, in this mode, the DRQ request is withdrawn by the I/O port and the TC output is activated. But the DACK* output is pulsed for each byte of data transfer. This scheme is used with fast peripherals like hard disk controller.