What is DMA?

DMA represents Direct Memory Access. It is a hardware-controlled data transfer technique. An external device is used to control data transfer. The external device generates address and control signals that are required to control data transfer. External devices also allow peripheral devices to directly access memory. The external device which controls the data transfer is called the DMA controller.

DMA Idle Cycle

When the system is turned on, the switches are in position A. The processor starts implementing the program until it requires to read a block of information from the disk. The disk processor transfers a sequence of commands to the disk controller to search and read the desired block of information from the disk.

When the disk controller is ready to transmit the information from the disk, it transfers a DMA request (DRQ) signal to the DMA controller. Thus the DMA controller sends a HOLD signal to the processor HOLD input.

The processor reply to this signal by suspending the buses and transferring an HLDA acknowledgment signal. When the DMA controller gets the HLDA signal, it transfers a control signal to modify the switch position from A to B.

DMA Active Cycle

When the DMA controller receives control of the buses, it transfers the memory address where the first byte of information from the disk is to be written. It also transfers a DMA to acknowledge (DACK) signal to the disk controller device signaling it to get ready to transfer the output byte.

Cycle Stealing Mode

In this data transfer mode, the device can make only one transfer (byte or word). After each transfer, DMAC gives the control of all buses to the processor. This is a single transfer mode with the process as follows −

  • I/O device asserts DRQ line when it is ready to transfer data.
  • The DMAC asserts the HLDA line to request the use of the buses from the processor.
  • The processor asserts HLDA, granting them control of buses to the DMAC.
  • The DMAC asserts DACK to the requesting I/O device and executes the DMA bus cycle, resulting in data transfer.
  • I/O device deasserts its DRQ after data transfer of one byte or word.
  • DMA deasserts DACK line.
  • The word/byte transfer count is decremented and the memory address is incremented.
  • The HOLD line is deasserted to give control of all buses back to the processor.
  • HOLD signal is reasserted to request the use of buses when the I/O device is ready to transfer another byte or word. The same process is then repeated until the last transfer.
  • When the transfer count is exhausted, the terminal count is generated to indicate the end of the transfer.