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Count registers of 8257
We have four Counters, ranging from CR3-0, which consists of 16 bits each. At the time when the CR becomes access to the processor which is 16-bits wide, the Least Significant and the Most Significant Byte of the register are accessed in an alternate manner, which starts with the Least Significant Byte. Also, the M/L* flip-flop helps here. The information about the number of bytes which are to be transferred using DMA are contained in the Counter Registers, which is decremented by 1 for every byte in the DMA data transfer. When the Counter Register becomes 0, the last DMA data transfer results in activating the terminal count (TC) output by 8257. Among the four channels there is only one output reads The status port of 8257 are read by the processor to find out which channel is responsible for activating the output by the 8257.
Although a Counter Register is 16-bits wide, only the 14 Least Significant bits of the register are used to specify the number of bytes which are to be transferred using Direct Memory Access scheme. So for data transfer maximum 214 = 16K = 16,384 bytes can be programmed. Suppose N is the number of bytes to be transferred using DMA data transfer, here we have to load (N-1) bytes in the 14 Least Significant Bits of the Counter Register. If the Counter Register is already loaded with the 0 value in the 14 Least significant bits , only one byte will be transferred in the process.
The type of DMA transfer is specified by the Most Significant 2 Bits of a Counter Register. It can be read by Direct Memory Access and also written to DMA and verified. The table below helps to understand the operations of Bit 15 and Bit 14.
|Bit 15||Bit 14||Operations|
In the given table, when bit 15 is equal to 1, the 8257 generates an MR* and IOW* signals. When bit 14 is equal to 1, it generates MW* and IOR* signals. Now in the table below when both the two bits Bit 15 and Bit 14 are 0 verification is done by DMA, When Bit 15 is 0 and Bit 14 is 1 the DMA reads the content. When bit 15 is 1 and Bit 14 is 0 the DMA writes. When both the bits are 1 it is an illegal operation and is not done.
|Bit 15||Bit 14||Operations|
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