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Description of 8257 DMA controller chip
As per DIP package Intel 8257 DMA controller chip is a 40-pin programmable Integrated Circuit. The pin diagrams of physical and functional are indicated below. The DMA controller chip 8257 works in two modes namely slave mode and master mode. Likely the processor also works in two modes namely active mode and HOLD mode. The processor normally works in active mode where the processor works as the master of the computer system. The processor goes to the HOLD state only when DMA transfer is required and it gives control to the system bus.
When the processor is programming 8257 it is in slave mode. But at the time of reading the internal memory of the register it is in active mode and becomes the master of the computer system.
8257 is used to control the DMA data transfer since it consists of four I/O ports. Every I/O port corresponds to a DMA channel. There is a DMA request called as DRQ input for every DMA channel, which corresponds DMA acknowledge as output. Amidst each DMA channel consists of 16-bit address register and 16-bit count register.
Fig. Physical pin diagram of Intel 8257
Fig: Functional pin diagram of Intel 8257
For performing the DMA data operation DMA channel has two lines HOLD and HLDA. When the I/O port needs MA service, it activates an input DRQ of 8257, which sends the Hold Request HRQ of 8085. The 8085 completes the current machine cycle and goes to the HOLD state. In this state the address pins and data pins like RD*, WR*, and IO/M* pins are tristate and attached. So in 8085 is effectively disconnected from the rest of the system.
Condition when processor is the master and 8257 is in slave mode
For communication between the processor and internal register of 8257, D7-0/A15-8 are the bi-directional data lines are used. The input lines A3-0 are used to select internal register of 8257 for communication with the processor.
IOR* and IOW*are the input lines of 8257 that the processor reads and writes to the internal registers of 8257.
The output pins of 8257 are MR*, MW*, and A7-, that are tristate by 8257.
Condition when processor is in the hold state and 8257 is in master mode
D7-0/A15-8 lines are used as uni-directional address output lines for sending out the Most Significant Byte of the address from 8257.
The output lines of 8257 are A3-0 which are used to send out the Least Significant 4 bits of address in 8257. Output lines of 8257 are A7-4 which are used to send out the most significant bits in 8257.
The output pins of 8257 are IOR*, IOW*, MR* and MW*. If the operation required is DMA read machine cycle the signals MR* and IOW* will be activated by 8257. The signals IOR* and MW* becomes in the inactive state. If the operation required is DMA write machine cycle the signals IOR* and MW* signals gets activated by the 8257. But the signals MR* and IOW* gets into inactive state. These are the conditions when the processor remains in Hold State and 8257 stays in Master Mode.
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