What is Asynchronous Communication Interface in computer architecture?

Computer ArchitectureComputer ScienceNetwork

The block diagram of an asynchronous communication interface is displayed in the figure. It works as both a sender and a receiver. The interface is boot up for a specific mode of transfer using a control byte that is loaded into its control register. The transmitter register receives a data byte from the CPU by the data bus. This byte is sent to a shift register for serial transmission.

The receiver portion receives serial information into another shift register, and when a finalize data byte is acquired, it is moved to the receiver register. The CPU can choose the receiver register to read the byte through the data bus. The bits in the status register are utilized for input and output flags and for recording specific errors that can appear during the transmission.

The CPU can read the status register to determine the status of the flag bits and to decide if any errors have appeared. The chip chooses and the read and write control lines connect with the CPU. The chip select (CS) input can select the interface by the address bus.

The register select (RS) is related to the read (RD) and write (WR) controls. Two registers are write-only and two are read-only. The register selected is a service of the RS value and the RD and WR status, as recorded in the table following the diagram.

CSRSOperationRegister Selected
0XXNone : Data bus in high impedance
10WRTransmitter Register
11WRControl Register
10RDReceiver Register
11RDStatus Register

The operation of the asynchronous communication interface is boot up by the CPU by sharing a byte to the control register. The initialization process locates the interface in a particular mode of operation as it represents specific parameters including the baud rate to use, how many bits are in each character, whether to create and check parity and how many stop bits are joined to each character.

Two bits in the status register are used as flags. One bit can signify whether the sender register is null and another bit can signify whether the receiver register is full.

The operation of the transmitter portion of the interface is as follows. The CPU reads the status register and determines the flag to view if the sender register is null. If it is null, the CPU sends a character to the sender register and the interface clears the flag to denote the register full.

The first bit in the transmitter shift register is set to 0 to create a start bit. The character is shared in parallel from the transmitter register to the shift register and the suitable number of stop bits are joined into the shift register. The sender register is then signified null. The character can now be sent one bit at a time by transferring the information in the shift register at the definite baud rate.

raja
Published on 24-Jul-2021 07:03:03
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