RAM Addressing of 8051 Microcontroller

Here we will see how external RAM memories can be addressed by the Intel 8051 microcontroller. There are different methods for addressing the RAMs. Now at first we will discuss about some different types of RAM memories in short.

The RAM (Random Access Memory) is volatile memory. So when the power is cutting off to the RAM chip, it losses the data. RAMs are also known as RAWM (Read and Write Memory). There are basically three kinds of RAMs. These are SRAM (Static RAM), NV-RAM (Non-Volatile RAM) and DRAM (Dynamic RAM).

Static RAM

The storage cell in Static RAM are made of flip-flops. It does not require any refreshing to keep their data. The main problem of Static RAM is, each flip-flops in this type of RAMs takes at least six transistors to build. But one flip-flop can hold only 1-bit data. So per bit of data we need six transistors. Even if now the flip-flops are made of four transistors but it is still too much. So the main problem is the cost. For a high capacity SRAM, it needs huge cost for development.


This is a new type of RAM. It is called the Non-Volatile RAM. It supports read and write operations by the processing unit, but when the power is turned off, the contents are not lost. It has the following components to store the data inside it.

  • It uses extremely power efficient SRAM cells, which are made off CMOS.

  • It uses an internal lithium battery as a backup energy source.

  • It has some advanced and intelligent control circuitry. This circuitry continuously checks whether the Vcc pin constantly getting power from external power sources or not. If the external power is not sufficient, then it automatically switches the power source from external source to internal source.

All of the mentioned conditions are incorporated into a single RAM chip. For these the NV-RAMs are too expensive. If we do not consider the costs, then it is very useful. One NV-RAM can store the data up to ten years when power is turned off.

Dynamic RAM

In 1970, Intel introduced the first dynamic RAM. The density of the first DRAM was 1024-bits. It uses capacitors to store each bit. By using the capacitors, the cost per bit is reduced. In the DRAM, they have to incorporate another task. That is the refreshing. The refreshing is needed for DRAM due to leakage. The main advantage of the Dynamic RAM is that, it can store more bits in a single unit of space, so the density high so the cost per bit is low. The main disadvantage is; it needs refreshing periodically because the capacitor cell loses its charges.

Internal RAM of 8051 Microcontroller

As we know the 8051 has 128-bytes of internal RAM from location 00H to 7FH. These 128-bytes of space is also divided into some other parts. These are as follows

  • The first one is 32-bytes of working registers. The address range is 00H to 1FH. These 32-bytes of spaces are again divided into four register banks.

    • Register Bank 0. Address range (00H to 07H)

    • Register Bank 1. Address range (08H to 0FH)

    • Register Bank 2. Address range (10H to 17H)

    • Register Bank 3. Address range (18H to 1FH)

  • The second part is 16-bytes of bit addressable registers. It ranges from 20H to 2FH.

  • The last part is 80-bytes of general purpose area. This space also used as a stack. It ranges from 30H to 7FH.

External RAM addressing of 8051 Microcontroller

The 8051 has only 128-bytes of internal RAM. So if we want to expand the RAM memory, we have to use the external RAMs with proper addressing schemes. In 8051, the pin P3.7 is used for Reading signal (RD) and the pin P3.6 is used for Write signal (WR). These read and write pins are connected to the RAM for reading and writing data. The port P2 (8-bit) is used for higher order 8-bit addressing, and port P0 (8-bit) is used for lower order addressing. The lower order 8-bit (P0) can also be used as a data bus. For the multi-tasking facility, we need another chip called 74LS373 to hold the lower order addresses while the port P0 is acting like data bus. The higher order address pins can be used for chip selection in case of multiple RAMs.

In this diagram, we are using 16K-bytes of external RAM. For 16K it needs 14-bits for address selection. Other two pins A14 and A15 are connected to the chip enable (CE) pin of the RAM chip.

Updated on: 27-Jun-2020

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