Interrupt structure of 8051

Microprocessor8085

Now in this section, we will see the interrupt structure of Intel 8051 microcontroller.

Interrupts are basically the events that temporarily suspend the main program, pass the control to the external sources and execute their task. It then passes the control to the main program where it had left off.

8051 has five interrupts. These interrupts are INT0,  INT1,TO ,T1 , TI/RI. All of the interrupts can be enabled or disabled by using the IE (interrupt enable) register.

The interrupt addresses of these interrupts are like below −

Interrupt
Address
INT00003H
INT1000BH
T00013H
T1001BH
TI/RI0023H


Interrupt Enable (IE)Register

This register can be used to enable or disable interrupts programmatically. This register is an SFR. The address is A8H. This byte is bit addressable. So it can be programmed by the user. The bits in this register has a different meaning. The register structure is looking like this:

BitAddress
AF
AE
AD
AC
AB
AA
A9
A8
Bit Details
EA
X
X
ES
ET1
EX1
ET0
EX0


Now, let us see the bit details and different operations when the value is low (0) and high(1).

Bit Details
High Value(1)
Low Value(0)
EA
Least significant 5 bits can decide enable or disable of these five interrupts.
Disable all five interrupts. It just ignores the rest five bits.
ES
Enable Serial Port Interrupt
Disable Serial Port Interrupt
ET1
Enable Timer1 interrupt
Disable Timer1 interrupt
EX1
Enable external interrupt 1 (INT1)
Disable external interrupt 1 (INT1)
ET0
Enable Timer0 interrupt
Disable Timer0 interrupt
EX0
Enable external interrupt 0 (INT0)
Disable external interrupt 0 (INT0)



Interrupt Priority (IP) Register

All of these five interrupts can be in one or two interrupt level. The priority levels are level 1 and level 0. Priority level 1 indicates the higher priority, and level 0 indicates lower priority. This IP register can be used to store the priority levels for each interrupt. This is also a bit addressable SFR. Its address is B8H. 

BitAddress
BF
BE
BD
BC
BB
BA
B9
B8
Bit Details
X
X
X
PS
PT1
PX1
PT0
PX0


Now, let us see the bit details and different operations when the value is low (0) and high(1).

Bit Details
High Value(1)
Low Value(0)
PS
Set 1 level priority of Serial port interrupt
Set 0 level priority of Serial port interrupt
PT1
Set 1 level priority of Timer1 interrupt
Set 0 level priority of Timer1 interrupt
PX1
Set 1 level priority of external interrupt 1 (INT1)
Set 0 level priority of external interrupt 1 (INT1)
PT0
Set 1 level priority of Timer0 interrupt
Set 0 level priority of Timer0 interrupt
PX0
Set 1 level priority of external interrupt 0 (INT0)
Set 0 level priority of external interrupt 0 (INT0)


When all of the five interrupts are in same priority level, and if all of the interrupts are enabled, then the sequence of interrupts will be INT0, T0, INT1, T1, TI/R I. 

Some specific priority register value can be used to maintain the priorities of the interrupts. Let the value of Priority register is xxx00101 indicates the sequence INT0, INT1, TI/RI, T1, T0. But all of the sequences are not feasible. Like INT0, INT1, TI/RI, T1, T0 is not valid.


External Interrupt

The external interrupts of 8051 are INT0and. INT1 These interrupts can be programmed to either edge-triggered or level triggered. The TCON register can be used top rogram external interrupts to edge or level triggered. The TCON isTimer Control. TCON is another bit addressable SFR. Here the address is 88H.

BitAddress
8F
8E
8D
8C
8B
8A
89
88
Bit Details
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0


Now, let us see the bit details and different operations when the value is low (0) and high(1).

Bit Details
High Value(1)
Low Value(0)
IT0
Set ( INT0) as negative edge triggeredinput.
Set ( INT0) as active low level triggered input.
IT1
Set ( INT1) as negative edge triggeredinput.
Set ( INT1) as active low level triggered input.
IE0
This will be 1, when INT0is activated as level triggered.
This will be 0, when INT0is activated as edge triggered.
IE1
This will be 1, when INT1 is activated as level triggered.
This will be 0, when INT1 is activated as edge triggered.
TR0
Set Timer0 as run mode
Set Timer0 as stop mode.
TR1
Set Timer1 as run mode
Set Timer1 as stop mode.
TF0
High when Timer T0 overflow occurs.
After resetting the timer T0 thiswill also be changed to 0 state
TF1
High when Timer T1 overflow occurs.
After resetting the timer T1 this will also be changed to 0 state.


The IT0 and IT1 are stands for Interrupt Type. These bits are used to decide whether the INT0 and INT1 will be level trigged or edge triggered.

IE0 and IE1 bits are used to indicate the status of external interrupts. These bit can be set or reset by the microcontroller itself.

The first four bits are the status information about timers. When TR0 and TR1 are 1, it indicates the running mode of the timers. These bits provide software control over the running of timers. Timers can also be controlled by the hardware. The priority of hardware mode is higher than the software mode. 

The TF0 and TF1 are used to indicate the overflow of timer T0 and T1 respectively. When over flow occurs these flags are set to 1. When the interrupt is handled by some interrupt service subroutine (ISS), these will be 0.

Serial Port Interrupt

The serial ports can be used either Transmitting mode or reception mode. The interrupt status for the Transmission is provided by TI, and status for Reception is provided by RI. These are two bits of SCON(Serial Control). This is also a bit addressable SFR. The address is98H

BitAddress
9F
9E
9D
9C
9B
9A
99
98
Bit Details
SM0
SM1
SM2
REN
TB8
RB8
TI
RI


The significance of these bits are as follows

Bit Details
Description
SM0
This is Serial Port Mode 0 shift register
SM1
This is Serial Port Mode 1 (8-bit UAR + variable)
SM2
Enable multiprocessor communication in the mode 2 or 3
REN
Set or reset by the software to enable or disable the Reception
TB8
It indicates the 9th bit that will be transmitted in mode 2 or 3. It can be set or reset by the software
RB8
In mode 2 or 3, the 9th bit was received in mode 1.
TI
The transmission interrupt flag. It can be set by hardware.
RI
The receiver interrupt flag. It can be set by hardware but must be reset by software.


The interrupt control system of 8051 is like below −


raja
Published on 31-Dec-2018 16:19:24
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