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Interrupt structure in Z-80
As we know that the Intel 8085 has five interrupt pins (TRAP, RST7.5, RST6.5, RST6.5 and INTR), but the Zilog Z-80 has only two interrupt pin. The NMI and INT . But it has superior interrupt structure compared to 8085.
The INT Interrupt
It is an active low, level triggered input interrupt. This is maskable and using DI instruction this can be disabled. When the interrupt pin is disabled, the Z-80 will not be interrupted if the IO devices enables the INT pin. Even after the reset, it will be disabled. So if we want that the MPU will be interrupted by the pin, there must be EI instruction in the program.
There are three interrupt mode, on which different actions take place after the interrupt using INT pin. These modes are Mode 0, Mode 1, and Mode 2.
Interrupt Mode 0 (IM 0)
It is a 2-byte instruction of Z-80. The opcode is ED 46H. After executing this instruction, the INT input will act like IM 0. This is the default mode after reset.
This mode is like the INTR of 8085. So it is non-vectored interrupt. The MPU activates the IORQ and M1 to respond the interrupt.
So the flow of INT in IM 0 (Assuming the NMI is not active, and EI instruction is executed to enable the interrupt system) is as follows −
- It completes the current instruction, then enables INT the M1 and
- Receives an RST or a CALL instruction from the peripherals
- Disables the Interrupt System
- Push the Program Counter value into the stack
- Jump to ISS (Interrupt Service Subroutine), indicated by the peripheral.
So here is a sample of 8085 and Z-80 ISS structure
| 8085 Interrupt Service Subroutine | Z-80 Interrupt Service Subroutine |
|---|---|
| PUSH PSW | EXX |
| PUSH H | EX AF, AF’ |
| PUSH D | {Other part of ISS} |
| PUSH B | EX AF, AF’ |
| {Other part of ISS} | EXX |
| POP B | EI |
| POP D | RETI |
| POP H | |
| POP PSW | |
| EI | |
| RET |
Interrupt Mode 1 (IM 1)
It is a 2-byte instruction of Z-80. The opcode is ED 56H. After executing this instruction, the INT input will act like IM 1. This mode is similar to the RST 7.5, 6.5 and 5.5 of 8085 MPU. The interrupt in this mode is vectored interrupt.
In this mode, the IORQ and M1 are not in the active state. The CPU automatically disables the Interrupt System, so we do not need to use DI instruction explicitly. The CPU stores the Program Counter (PC) value to the stack top and jumps to location 0038H.
In Z-80 kit, if the 0038H is under the section of Monitor program, there must be one unconditional jump statement to jump to the actual subroutine section.
Interrupt Mode 2 (IM 2)
Another 2-byte instruction of Z-80 is ED 5EH. After executing this instruction, the INT input will act like IM 2. This is a special mode; this mode is not present in the 8085 MPU. The main feature of this mode is that as many as 128 interrupting sources could be present in the system. Among these sources, each source can send unique 1-byte address to the CPU to activate IORQ and M1 simultaneously. So according to the address, it can jump to different 128 service routines.
So we can summarize the steps in IM 2 −
Complete the current instruction execution
Activate IORQ and M1
Get 1-byte address from the peripherals and treat this as Least Significant Byte of address pointer after setting the LSb as 0. And the content of I register is treated as Most Significant Byte.
Disables the interrupt system
Save the Program Counter value to the Stack Top.
Jump to the Interrupt service subroutine, pointed by address pointer.
The NMI Interrupt
The NMI stands for Non-Maskable Interrupt. It is negative edge triggered input interrupt. It has higher priority than the INT . This interrupt is non-maskable, and also vectored. It is very similar to the TRAP of 8085. It jumps to the memory location 0066H, when this interrupt is generated. Like TRAP, the NMI is used for high priority conditions, like power failure etc. After returning from the NMI service routine, the system will be restored to the earlier enabled or disabled state.
So we can summarize the steps of NMI −
- Complete the current instruction execution
- Disables the interrupt system
- Store Program Counter value at the top of the stack
- Jump to the location 0066H
In Z-80 kit, if the 0066H is under the section of Monitor program, there must be one unconditional jump statement to jump to the actual subroutine section. The NMI service routine will contain these steps −
- Save all register contents into the stack top
- Perform the required action to satisfy the interrupting devices
- Pop all register content from the stack top
- Return to the main program by using RETN instruction.
Using RETN (Return from NMI interrupt), the Program counter value will be restored from the stack top to return to the main program, and go back to the old value of interrupt enable/disable status.
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