- Trending Categories
- Data Structure
- Operating System
- MS Excel
- C Programming
- Social Studies
- Fashion Studies
- Legal Studies
- Selected Reading
- UPSC IAS Exams Notes
- Developer's Best Practices
- Questions and Answers
- Effective Resume Writing
- HR Interview Questions
- Computer Glossary
- Who is Who
Interrupt handing in 8051
As we have seen there are five different interrupts in 8051. These interrupts are INT0, INT1, TO, T1, TI/RI.
There are six states in each machine cycle. These states are S1 to S6. All of the interrupts are sampled at the end of state S5 of each machine cycle. When the instruction takes more than one machine cycle, then the samples are polled during the next machine cycle. When an interrupt flag is set at the S5 of the first machine cycle, then the polling cycle will find it. The interrupt system generates LCALL instruction to call appropriate ISS.
There are some conditions. When the none of these conditions are satisfied, then only that operation could be performed. These conditions are as follows −
When an interrupt with equal or higher priority is already in progress.
When the polling cycle is not the final machine cycle in the execution of the current instruction.
When the current instructions are not
Writing to IP register
Writing to IE register
When any one of these conditions is true, the LCALL to the Interrupt Service Subroutine(ISS) will not be generated. The second condition tells that the current execution is completed before branching to an ISS. The last condition tells that at least one more instruction is executed after the RETI instruction or any writing instruction to IE or IP register before executing the ISS.
When one ISS is executing, the microcontroller can be interrupted by higher priority interrupts. If the priority level is already 1, the microcontroller cannot be interrupted. When it finishes the ISS execution, then the only new interrupt can occur.
When one ISS is called, the Program Counter (PC) value will be pushed into the stack. After execution of the ISS, the RETI instruction is executed. So after executing RETI, the PC value is popped from the stack to go back to the next instruction where the control is switched. If the ISS ends with RET but not with RETI, then the microcontroller thinks that the interrupt is still in progress.
Single Step Operation of 8051 Microcontroller
This 8051 supports single-step execution of a program. We can use the external interrupt pin as a key input. Let us consider the pin INT0 is connected with a key. At first, the interrupt pin value is 0, when the key is pressed, then the value is 1, and after releasing the key, it will become 0 again.
This key can be a single step key. The INT0 is programmed to be a level-triggered interrupt. TheInterrupt Service Subroutine (ISS) is terminated with the following code for the single-step action.
The P3.2 bit is used as INT0 pin.
L1:JNBP3.2, L1 L2:JBP3.2, L2 RETI
The first line indicates that it will be in L1, till INT0 becomes 1, and the second line indicates it will be in L2 till INT0 becomes 0. And the RETI indicates to return to the main program from the ISS.
- Related Articles
- Interrupt structure of 8051
- Interrupt structure in Z-80
- Interrupt request register in 8259
- Interrupt mask register in 8259
- Trap interrupt pin in 8085
- 8051 Microcontroller
- Arithmetic group in 8051
- Logical Group in 8051
- Interrupt-driven data transfer in 8085
- Data transfer group in 8051
- Bit-processing group in 8051
- Program branch group in 8051
- Bit manipulation program in 8051
- Timers of 8051
- Difference Between Interrupt and Polling in OS