An 8-bit register in which the tracks of active interrupt requests are kept. Whenever activation of an interrupt request input is done the bit corresponding in IRR register is set to 1. For example, if we activate the IR4 and IR6 inputs bits no 4 and 6 of IRR are set to 1 by making the contents of IRR as 01010000. But the processor is designed only to read the contents of this register but cannot write it to IRR. To read the IRR contents, the processor only has an issue the OCW3 command to the 8259 along with the LS 3 bits of the command. This results in 8259 by storing the IRR status in the low port of 8259. Sothe processor has to read the low port of 8259.
Fig:8259 interfaced along with 8085 processor