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The PentiumPro is the flagship of Intel’s x86 line of processors. The Pentium Pro processor performs a dynamic implementation microarchitecture such as a specific set of multiple branch prediction, data flow analysis, and speculative implementation. The Pentium Pro processor has a decoupled, 12- phases, super pipelined implementation, trading less work per pipestage for more phases.The Pentium Pro processor also has a pipestage time of 33 percent less than the Pentium processor, which supports obtain a higher clock value on any given process. The method utilized by the Pentium Pro processor eliminates the constraint of linear instruction sequencing between the traditional ... Read More

The PowerPC 620 is the highest performance model of the PowerPC line. It is the first chip for the application server and high-tech office product line inside the PowerPC family. It uses a high-execution microarchitecture with several advanced superscalar features to exploit instruction-level parallelism.The PowerPC 620 has six EUs capable of parallel operations. These units are as follows − a branch processing unit (BPU), two simple integer units (IU1 and IU2) performing one-cycle integer and logical operations, a single multi-cycle integer unit (MIU) performing mainly integer multiplications and division, a load/store unit (L/SU) and an FP unit (FPU).Features of PowerPC ... Read More

The MIPS R10000 is the latest architecture of the R line of processors. It implements the MIPS IV ISA (Instruction Set Architecture), which is a superset of the MIPS III, supported for instance by the R8000. At a planned clock rate of 200 MHz, this four-way superscalar processor has a peak performance of 800 MIPS.Features of R10000The R10000 has the following main features which are as follows −It is a four-way superscalar processor with a maximum dispatch rate of five.It uses pre-decoding.It has three group reservation stations.Operands are fetched about instruction dispatch.Renaming is implemented using a merged architectural and rename ... Read More

ROB stands for reorder buffer. The ROB was first expressed by Smith and Pleszkun in 1988. They conceived the ROB to solve the precise interrupt problem. The ROB is a round buffer with head and tail pointers.The head pointer denotes the area of the next complimentary entry. Instructions are written into the ROB in strict program order. As instructions are issued, a new entry is designated to each in sequence.An instruction is enabled to retire only if it has been completed and all earlier instructions are previously retired. This approach provides that instructions retire strictly in order. Sequential consistency is ... Read More

Load and store instructions involve actions affecting both the processor and the memory. While executing, both load and stores must first wait for their addresses to be computed by an ALU or address unit. Then, loads can access the data cache to fetch the requested memory data which is then made available in a register. The load is then completed usually by writing the fetched data into the specified architectural register.Stores have a different execution pattern. After receiving their generated addresses, stores have to wait for their operands to be available. Unlike other instructions, a store is considered to be ... Read More

Sequential consistency of instruction execution associates with two techniques such as first to the order in which instructions are finished and second to the order in which memory is created because of the load and store instruction or memory references of other instructions as shown in the figure.The term processor consistency indicates the consistency of instruction completion with sequential instruction execution. Superscalar processors preserve either a weak or strong consistency.A weak processor consistency means that instructions can complete out-of-order, provides that no data dependencies are satisfied. In this case, instructions may be reordered by the processor only if no dependencies ... Read More

The design space of register renaming resembles that of shelving. As shown in the figure, it consists of the following main components such as the scope of register renaming, the layout of rename buffers, the operand fetch policy, and the number of renames per cycle.Scope of Register RenamingMost first-generation superscalar processors, like the PA 7100, Supersparc, α21064, R8000, Pentium, and others did not employ renaming. In partial renaming, it is restricted to a particular instruction type or a few types. Examples are the Power1 (RS6000), Power2, and Nx586.Layout of the rename buffersThe layout of the rename buffers creates the real ... Read More

When instructions are executed in parallel, they will be completed in out-of-program order. Here, it does not matter whether instructions are issued or dispatched in order or out-of-order, or whether shelving is used or not. The point is that unequal execution times force instructions to finish out-of-order, even if they are issued (and dispatched) in order. Then short, ‘younger’ instruction can be completed previous than long, ‘older’ ones. Thus, superscalar instructions give rise to an out-of-order finishing of instructions.Here, it can make a distinction between the terms ‘to finish’, ‘to complete’, and ‘to retire’ an instruction. The term ‘to finish’ ... Read More

There are four different methods to implement rename buffers such as using a merged architectural and rename register file, employing a separate name register file, or holding renamed values either in the ROB or in DRIS.In the first method, rename buffers are executed along with the architectural registers in a similar physical register file, known as the merged architectural and rename register file. The merged register file has to provide a large enough number of physical registers to implement both the architectural and rename registers. For instance, the Power1 provides 40 and the R10000 64 physical registers for renaming 32 ... Read More

The layout of the rename buffers establishes the actual framework for renaming. There are three basic components are the type and the number of the rename buffers and the basic mechanism which is used for accessing rename buffers as displayed in the figure.Type of rename buffersThe chosen type of rename buffers has the largest impact on renaming. It is definitive for the basic approach of the implementation and thus it determines where the intermediate results of the instruction are to be written into or read form. It can be designated as intermediate results which have already been generated but are ... Read More