Found 826 Articles for Network

In a static network, the connection between input and output nodes is fixed and cannot be modified. Static interconnection network cannot be reconfigured. Examples of this network are linear array, ring, chordal ring, tree, star, fat tree, mesh, tours, systolic arrays, and hypercube. The design space for static interconnection topologies is shown in the figure.Linear ArrayThis is a most elementary interconnection design. In this processors are linked in a linear one-dimensional array. The first and last processors are linked with one adjacent processor and the middle processing components are linked with two adjacent processors. It is a one-dimensional interconnection network.RingThis ... Read More

Direct Interconnection networks are used to connect different processing elements or different process memory. Interconnection networks are also known as multi-stage interconnection networks (or MINs), are high-speed computer networks.Characteristics of Direct Interconnection NetworkTopology − It denotes how the nodes of a network are organized.Network Diameter − It is the minimum distance between the most distant nodes in a network. The distance is measured in terms of the multiple specific hops between any two nodes.Node degree − The number of edges linked with a node is known as node degree. If the edge carries information from the node, it is known ... Read More

Shared Memory MIMD Architectures is known as Multiprocessor. It can consider a set of processors and a set of memory modules. Any processor can directly access any memory module through an interconnection network as displayed in the figure. The set of memory modules represent a global address space that is shared by all processors. This type of parallel machine is called Shared Memory MIMD Architectures.Advantages of Shared Memory MIMD ArchitecturesThere are the following advantages of shared memory MIMD architectures are as follows −There is no requirement to partition either the code or the data, thus uniprocessor programming methods can simply ... Read More

Distributed memory MIMD Architecture is known as Multicomputer. It can replicate the processor/memory pairs and link them through an interconnection network. The processor/memory pair is known as the processing element (PE) and PEs work more or less separated from each other.Whenever interaction between them is possible through message passing one PEs cannot directly access the memory of other PE. This class of MIMD machines is known as distributed memory MIMD architectures or message passing MIMD architectures.In distributed-memory MIMD machines, each processor has its memory location. Each processor has no explicit knowledge about other processor's memory. For data to be transmitted, ... Read More

Guarded execution is a means to eliminate; at least partly, conditional branches. The idea is to introduce conditional operate instructions into the architecture and use them to replace conditional branches. Conditional operate instructions are called guarded instructions. A guarded instruction consists of two parts, a conditional part called the guard and an operational part which is a traditional instruction. It can be expressed, for instance, in the form −(guard) instructionThe execution of guarded instruction depends on the following condition: if the specified guard is true, the associated instruction will be executed; if the guard turns out to be false, the ... Read More

Multiway branching is another possibility for reducing branch penalties. With multiway branching, both the sequential and the taken paths of an unresolved conditional branch are pursued, as shown in the figure. The multiway branching requires multiple program counters (PCs) referred to as IFA1 and IFA2 in the figure.Once the specified condition is resolved, which of the paths is correct becomes evident. If the correct path is the sequential one, its execution will be confirmed and the taken path execution discarded, consequently, IFA1 contains the correct continuous address. In the opposite case, vice versa.During speculative execution of a conditional branch, a ... Read More

Branch processing comprises basic tasks, such as instruction fetch, decode and BTA calculation, and possibly additional dedicated tasks to speed up branch processing. These dedicated tasks may be early branch detection, branch prediction, or an advanced scheme for accessing target paths.Usually, the dedicated tasks are executed using dedicated hardware, like a BTAC, BTIC, or BHT. There are two methods to the basic tasks. All earlier pipelined processors and many recent processors execute branches by utilizing the pipeline stages available for common instruction processing as shown in the figure −By contrast, some recent processors provide a separate unit, usually called a ... Read More

This is the latest scheme introduced to access branch targets, employed in a few recently announced processors such as the Am29000 superscalar, K5, and UltraSparc. Here, the basic idea is to append, for each line in the I-cache, a successor index that points to the next line to be fetched as shown in the figure. In all the processors, each cache line can contain 16 bytes of instructions.This means that a cache line holds in the AM29000 superscalar and the UltraSparc four instructions, whereas in the x86-compatible K5 a variable number of CISC instructions. The successor index is fetched in ... Read More

This scheme is only used occasionally, in cases when the taken penalty would be intolerable high due to a longer than I-cache latency. The basic idea of the BTIC scheme is to provide a small extra cache that delivers, for taken or predicted taken branches, the branch target instruction or a specified number of BTIs, rather than the BTA. Thus, otherwise unused pipeline cycles can be filled with target instructions.There are two alternatives implementations of the BTIC scheme, as shown in the figure. In the first, the address of the continuation of the taken path is also stored in the ... Read More

This scheme employs a more cache, known as the branch target address cache (BTAC), for speeding up access to branch targets as shown in the figure. The BTAC includes a group of currently used branch addresses and branch target addresses and is accessed relatively.When the actual instruction fetch address is a branch address, and there is an equivalent entry in the BTAC, the branch target address is fetched along with the branch instruction in a similar cycle. This BTA is then used to access the branch target instruction in the next cycle.The Branch Target Address Cache (BTAC) includes branch target ... Read More