Found 826 Articles for Network

One of the most famous interconnection networks is the single shared bus. Firstly, its organization is simply a generalization and extension of the buses employed in uniprocessors and some additional ones to solve the contention on the bus when several processors simultaneously want to use the shared bus. These lines are called arbitration lines and play a crucial role in the implementation of shared buses.Secondly, the shared bus is a very cost-effective interconnection scheme. It can be raising the number of processors does not improve the price of the shared bus. However, the contention on the shared bus represents a ... Read More

COMA stands for Cache-only memory access machines. A COMA machine includes several processing nodes connected by an interconnection network. Each processing node has a high-implementation processor, a cache, and an allocation of the global shared memory.COMA machines try to avoid the problems of static memory allocation of NUMA and CC-NUMA machines by excluding main memory blocks from the local memory of nodes and employing only large caches as node memories. In these architectures only cache memories are present; no main memory is employed either in the form of a central shared memory as in UMA machines or the form of ... Read More

CC-NUMA stands for Cache-coherent non-uniform memory access machines. A CC-NUMA machine includes several processing nodes linked through a high-bandwidth low-latency interconnection network. Each processing node includes a high-implementation processor, the related cache, and an allocation of the global shared memory.Cache coherence is preserved by a directory-based, write-invalidate cache coherence protocol. It can maintain all caches consistent, every processing node has a directory memory corresponding to its allocation of the shared physical memory.For each memory line, the directory memory saves recognizes remote nodes caching that line. Thus, utilizing the directory, it is applicable for a node writing a location to send ... Read More

Cray T3D is the most recent NUMA machine that was designed to provide a highly scalable parallel supercomputer that can incorporate both the shared memory and the message-passing programming paradigms. As in other NUMA machines, the shared memory is distributed among the processing elements to avoid the memory access bottleneck and there is no hardware support for cache coherency. However, a special software package and programming model, called the CRAFT, manages coherence and guarantees the integrity of the data.The Cray T3D hardware structure is divided into three parts are as follows −MicroarchitectureMacroarchitectureThe microarchitecture is based on Digital’s 21064 Alpha AXP ... Read More

Hector is a hierarchical NUMA machine consisting of stations connected by a hierarchy of ring networks. Stations are symmetric multiprocessors where the processing modules are linked by an individual bus. Nodes comprise three main units − a processor/cache unit, a memory unit, and the station bus interface which connects the otherwise separated processor and memory buses.The separation of two bus enables other processors to access this memory while the processor performs memory access operations in off-node memory. The processing modules of the machine are grouped into shared bus symmetric multiprocessors, called stations. These are connected by bit-parallel local rings, which ... Read More

NUMA represents Non-uniform Memory Access. NUMA is a multiprocessor model in which each processor is connected with the dedicated memory. Non-uniform memory access (NUMA) machines were intended to prevent the memory access bottleneck of UMA machines. The logically shared memory is physically assigned among the processing nodes of NUMA machines, leading to distributed shared memory architectures.These parallel computers became hugely scalable, but they are very responsive to data allocation in local memories. Accessing a local memory segment of a node is much quicker than accessing a remote memory segment.The main difference is in the organization of the address space. In ... Read More

UMA represents Uniform memory access. It is a shared memory architecture used in parallel computers. All the processors in the UMA model share the physical memory uniformly. In UMA architecture, access time to a memory location is autonomous of which processor creates the request or which memory chip includes the shared data.Although the UMA architecture is not suitable for building scalable parallel computers, it is excellent for constructing small-size single bus multiprocessors. Two such machines are the Encore Multimax of Encore Computer Corporation representing the technology of the late 1980s and the Power Challenge of Silicon Graphics Computing Systems representing ... Read More

In adaptive routing, intermediate nodes can take the actual network conditions, including the presence of deterioration or bottlenecks, into account and decide accordingly which neighbor the message should be transmitted. Adaptive routing scheme can be either profitable or misrouting according to the selection of the output channel. In profitable routing, only channels that are known to be guaranteed to move closer to the destination are candidates for selection.Profitable routing represents a conservative view. Misrouting protocols rely on an optimistic view and can use both profitable and non-profitable channels for establishing a path between the source and destination. Selecting a non-profitable ... Read More

In deterministic routing, the path is fully determined by the source and destination nodes. Intermediate nodes are unable to direct messages even in the case of network congestion.Deterministic routing can be further classified according to the node position where the deterministic path is selected. In source routing, it is the source node that selects the complete path between the source and destination nodes. Distributed routing gives each intermediate node the freedom to independently determine the next node of the path to which the message should be sent. There are three deterministic routing schemes are as follows −Street-sign routing − Street-sign ... Read More

Switching is the actual mechanism by which a message is removed from the input buffer and placed in the output buffer. The switching technique applied has an over-whelming effect on message latency and hence the choice of switching method is crucial in designing any distributed memory computer. The design space of the switching technique is shown in the figure.Packet Switching (store and forward)In the first-generation multicomputer, the packet switching mechanism was borrowed from the world of computer networks. The packet switching mechanism behaves in a store and forward manner similar to the mail service. A message is divided into packets ... Read More