What is the difference between RISC and CISC in Computer Architecture?

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RISC represents Reduced Instruction Set Computer. In Reduced Instruction Set Computer (RISC) architecture, the instruction set of the computer is simplified to reduce the execution time. RISC has a small set of instructions, which generally include register-to-register operations. In RISC, all instructions have simple register addressing and hence use less number of addressing modes.


CISC represents Complex Instruction Set Computer. It comprises a complex instruction set. It incorporates a variable-length instruction format. Instructions that require register operands may take only two bytes.

If the computer has 32-bit words (four bytes), the first instruction occupies half a word, while the second instruction needs one word in addition to one byte in the next word. Packing variable instruction formats in a fixed-length memory word require special decoding circuits that count bytes within words and frame the instructions according to their byte length.

Let us see the comparison between RISC and CISC Processor.

Some of the instructions refer to memory.Most of the instructions refer to Memory.
There are few addressing modes. Most instructions have register to register addressing modes.There are many addressing modes.
There are few instructions.There are many instructions.
It can include simple instructions and takes one cycle.It can include complex instructions and takes multiple cycles.
Hardware executes the instructions.Micro-program executes the instructions.
There are Fixed format instructions.There are Variable format instructions.
It can be easier to decode as instructions have a fixed format.It can be complex to decode as instructions have variable format.
There are multiple register sets are used.A single register set is used.
RISC is highly pipelined.CISC is not pipelined or less pipelined.
It can load and store functions are separate instructions.It can load and store functions are found in a single instruction.
Published on 27-Jul-2021 12:44:59