A register adequate for changing its binary data in one or both directions is known as a shift register. The logical design of a shift register includes a series of flip-flops, with the output of one flip-flop linked to the input of the next flip-flop.
There are various modes of operations of shift registers which are as follows −
The controlling of shifting of information decides the ‘serial-in serial-out’ shift register into the right shift and left shift register. The diagram demonstrates a ‘serial-in serial-out’ right shift register.
During the first clock pulse, the signal on the data input is latched in the first flip-flop. During the next clock pulse, the substance of the first flip-flop is saved in the second flip-flop, and the signal which is available at the data input is saved in the first flip-flop, etc. Because the information is recorded one bit at a time, we call it a serial-in shift register. If there is only one output, and data leaves the shift register one bit at a time. It is also referred to as a serial-out shift register.
The ‘preset’ and ‘clear’ input commands can be supported to the flip-flops to access a parallel input. The parallel storing of the flip-flop can be synchronous or asynchronous rely upon the design of the shift register. The outputs of each flip-flop make a parallel output.
In this register, there is concurrent access of all information bits and the bits occur on parallel outputs concurrently. The following diagram demonstrates a ‘parallel in parallel out’ shift register.