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What are the basic components of the memory management unit in computer architecture?
In a multiprogramming system, the main memory is broken into two parts as one part for the operating system (resident monitor) ad one part for the program currently being implemented. In a multiprogramming system, the “user” part of memory is divided to contain various processes. The task of the subdivision is carried out dynamically by the operating framework and is called memory management.
Address spaces − The Pentium-II contains hardware for both segmentation and paging. Both mechanisms can be disabled, enabling the user to select from the definite aspect of memory −
Unsegmented unpaged memory − In this case, the virtual address is the equivalent of the physical address. This is useful in low complexity and high-performance controller application.
Unsegmented paged memory − In this case, memory is considered as a paged linear address space. Protection and management of memory are completed via paging.
Segmented unpaged memory − Memory is considered as a set of logical address spaces. It assurance that the translation table required is on-chip when the segment is in memory.
Segmented paged memory − Segmentation is used to describe logical memory division subject to access control, and paging can handle the allocation of memory inside the partitions. Segmentation and paging are completed in memory management hardware.
Segment Descriptor (Segment table entry)
Base − It describes the starting address of the segment inside the 4G byte linear address space.
D/B bit − In a code segment, this is the D bit and denotes either operands or addressing modes are 16 or 32 bits.
Descriptor privilege level (DPL) − It defines the privilege level of the segment described by the segment descriptor.
Granularity bit (G) − It denotes either the limit field is to be disrupted in units by one byte or 4K bytes.
S bit − It specifies whether a given segment is a system segment or a code or data segment.
Segment present bit (P) − It is used for non-page systems. It denotes whether the segment is existing in the main memory. For paged system, this bit is constantly set to 1
Type − It can determine between multiple types of segments and denotes the access attributes.
Page directory entry and Page table entity
Accessed bit − This bit is set to 1 by the processor in both levels of page tables when a read or write operation to the corresponding page appears.
Dirty bit − This bit is set to 1 by the processor when a write operation to the corresponding page appears.
Page Cache Disable bit − It indicates whether data from the page can be cached.
Page Size bit − It denotes whether the write-through or write-back caching policy will be utilized for data on the equivalent page.
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