Found 312 Articles for Computer Architecture

Superscalar processing can be broken down into several particular tasks, which is shown in the figure. Superscalar processors can issue multiple instructions per cycle, the first task certainly is parallel decoding.Decoding in superscalar processors is a significantly more complex task than in the case of scalar processors and evolves into even more sophisticated as the issue rate improves.Higher issue rates can immensely extend the decoding cycle or can provide growth to various decoding cycles unless decoding is increased. An increasing technique of improvement is pre-decoding.This is partial decoding implemented in advance of typical decoding, while instructions are loaded into the ... Read More

A superscalar processor is created to produce an implementation rate of more than one instruction per clock cycle for a single sequential program. Superscalar processor design defines as a set of methods that enable the central processing unit (CPU) of a computer to manage the throughput of more than one instruction per cycle while performing a single sequential program.While there is not a global agreement on the interpretation, superscalar design techniques involve parallel instruction decoding, parallel register renaming, speculative execution, and out-of-order execution. These techniques are usually employed along with complementing design techniques including pipelining, caching, branch prediction, and multi-core ... Read More

The concrete architecture at a given level is normally defined in the phrase of its components. Hence, the description of the concrete architecture at a given level is based on the abstract architectures of its components.As an effect, the concrete architecture at a specific level is a description at a higher abstraction level than the corresponding abstract architecture at the subsequent lower level.Thus, we can define that the sequence of theory of concrete and abstract architectures at successive levels yields a description framework at following higher levels of abstraction.Therefore, the three-level architecture description design considered, with independent concrete and abstract ... Read More

It can interpret the theory of computer architecture at several levels of rising abstraction. At each level, the architecture will be represented by declaring the underlying computational model, the functional specification, and the actual implementation. Therefore, the interpretation covers three elements including the underlying computational model, the level of consideration, and the scope of interest, as displayed in the figure.First, it can overview the underlying computational model. Several years in the past, the term ‘computer architecture’ was inherently interpreted as a von Neumann architecture.Subsequently, when novel architectures that depend on a model of computation other than the von Neumann model ... Read More

Von Neumann’s model is composed of three specific components (or sub-systems) including a central processing unit (CPU), memory, and input/output (I/O) interfaces. The figure defines one of the various possible methods of interconnecting these components.CPU − CPU can be regarded as the soul of the computing system, includes three main components: the control unit (CU), one or more arithmetic logic units (ALUs), and multiple registers. The control unit decide the order in which instructions should be implemented and controls the retrieval of the useful operands. It defines the instructions of the machine.The execution of each instruction is persistent by a ... Read More

There are six basic computational models such as Turing, von Neumann, dataflow, applicative, object-based, predicate logic-based, etc. These models are known as basic models because they can be declared using a basic set of abstractions.A hierarchy of subclasses can be defined for each of the basic models to any extent required. For instance, if the process abstraction is introduced into the von Neumann model, new subclasses can be defined according to whether all processes might have access to a global data space (Shared-memory subclass) or the processes could have their own local data spaces, and access remote data spaces by ... Read More

The theory of a computational model is a higher-level abstraction than the approach of programming language and computer architecture.A programming language can be speculation as a specification device making applicable the system of a computational task whereby a specific computational model is pretended.Computer architecture can be considered upon as a tool to execute a computational model or to implement a given computational task defined using a programming language, whereby a specific computational model is given.To demonstrate these relationships it can consider the basic features of the programming languages and computer architectures that compare to the von Neumann computational model.A programming ... Read More

The implementation of global instruction scheduling is a technique called trace scheduling. Trace scheduling was first employed in the Bulldog compiler, developed for the experimental VLIW machine ELI-512 at Yale (Fisher et al, 1984), and subsequently in the Trace scheduling compiler of the commercial TRACE family of VLIW machines (Colwell et al, 1987).A more recently published novel global schedule technique is FRGS (Finite Resource Global Scheduling), developed and experimentally implemented by IBM for VLIW and superscalar processor (Moon and Ebcioglu, 1992, Moon et al, 1993).Trace SchedulingThis technique originates like most instruction scheduling techniques, in the schedule for horizontally microcoded machines ... Read More

ILP-compilers have to extract acceptable instruction-level parallelism to make use of available hardware resources properly, specifically EUs. This is not a simple task for extremely parallel ILP-processors, including VLIW machines or highly superscalar processors. In specific, general-purpose programs, including operating systems or application programs, with their small fundamental block sizes and profoundly irregular parallelism, characterized using unpredictable branches make this task intensely hard or even unsolvable.In this method, basic block schedulers cannot be predicted to extract sufficient parallelism to feed hugely parallel ILP-processors accurately. Therefore, compilers for parallelism-greedy ILP-processors have to make use of the very effective scheduling techniques, known ... Read More

Software pipelining is a compile-time scheduling technique that overlaps consecutive loop iterations to disclose operation-level parallelism. A necessary issue with the development of adequate software pipelining algorithms is how to deal with loops with conditional branches.Conditional branches raise the complexity and reduce the performance of software pipelining algorithms by presenting few possible execution paths into the scheduling scope. Software Pipelining is implemented either by techniques based on unrolling or by modulo scheduling as shown in the figure.The basic idea of the techniques based on unrolling is quite simple − unroll the loop several times and arrange unrolled code in the ... Read More