Shelving buffers have three major aspects such as the type and capacity of the buffers used and the number of their read and write ports, as shown in the figure.
There are two generic types of shelving buffers such as standalone shelving buffers and combined buffers which are used for shelving, renaming, and reordering as shown in the figure.
In most cases shelving buffers are implemented as standalone shelving buffers, that is, buffers that are utilized particularly for shelving. This type of shelving buffer is usually designated reservation stations. In the superscalar processor, reservation stations are executed using three basic schemes, as shown in the figure.
In the simplest case, individual reservation stations are used at beginning of each EU. Therefore, instructions that are scheduled to be implemented in a specific EU are first shared into the related reservation station previous to that EU. Individual reservation stations support sufficient space to influence only a small number of instructions, say 2 to 4.
In a different method, reservation stations are executed as group stations. Therefore, the same reservation station holds instructions for an entire group of EUs, which implement instructions of a similar type. For example, the R10000 has three group stations, one of these serves two FX-ALUs, another a single address unit, while the third provides four FP units.
The final method is when a central reservation station serves all EUs. A central station requires to have a higher size than group stations. Moreover, it can accept and dispath several instructions per cycle than group stations.
The advancement from individual to group and then to central reservation stations carry with it the need to support an increasing number of shelving places. Individual reservation stations can shelve 2 - 4 instructions, group stations have 6, 12, or 16 entries, while the only execution so far of a central reservation station, the PentiumPro, can hold 20 instructions. The total number of entries in reservation stations offers accounts for the diameter of the dispatch window.
The final component of the layout of shelving buffers is the number of reads and write ports. This component determines how several instructions can be written into or read out from a specific shelving buffer in an individual cycle. First, let us treated the expected number of output ports (read ports).
Individual reservation stations require only forward a single instruction per cycle. A group or a central reservation station requires to deliver various instructions per cycle, perfectly as many as EUs are linked to it. The individual, group, and central reservation stations require increasingly more input ports (write ports). Processors with individual reservation stations provide enable only one instruction per cycle to be issued into anyone’s reservation station.