A superscalar processor is created to produce an implementation rate of more than one instruction per clock cycle for a single sequential program. Superscalar processor design defines as a set of methods that enable the central processing unit (CPU) of a computer to manage the throughput of more than one instruction per cycle while performing a single sequential program.
While there is not a global agreement on the interpretation, superscalar design techniques involve parallel instruction decoding, parallel register renaming, speculative execution, and out-of-order execution. These techniques are usually employed along with complementing design techniques including pipelining, caching, branch prediction, and multi-core in current microprocessor designs.
Superscalar processor emerged in three consecutive phases as first, the idea was conceived, then a few architecture proposals and prototype machines appeared, and finally, in the last phase, the commercial products reached the market.
The concept of the superscalar issue was first developed as early as 1970 (Tjaden and Flynn, 1970). It was later reformulated more precisely in the 1980s (Torng, 1982, Acosta et al, 1986).
Superscalar processor proposals and prototype machines followed as shown in the figure.
As far as prototype machines are concerned IBM was the first with two significant superscalar developments called the Cheetah and America project. The Cheetah project (1982-83) and the subsequent America project (from 1985 on) were the testbeds for IBM to study superscalar execution.
The four-way Cheetah machine served as a base for the America processor, which spawned the RS/6000 (1990), which was later renamed the Power1. The Power 1 is almost identical to the America machine (Grohoski, 1990).
The term superscalar processor is assumed to have first appeared in connection with these developments in an internal IBM Technical Report (Agarwala, T and Cocke, J. High-Performance Reduced Instruction Set Processors, 1987).
A second early player in the area of superscalar developments was DEC with its Multititan project, carried out from 1985 to 1987. While the Multititan project was the continuation of project Titan (1984), whose goal was to construct a very high-speed RISC processor, this project did not contribute much to the development of the α line of processors.
The Intel 960CA embedded RISC processor was the first commercial superscalar machine, introduced in 1989. To boost performance subsequently all major manufactures were forced to introduce the superscalar issue in their commercial processor lines.
Superscalar RISC processors emerged according to two different approaches. Some appeared as the result of transferring a current (scalar) RISC line into a superscalar one. Examples of this are the Intel 960, MC 88000, HP PA (Precision Architecture), SunSparc, MIPS R, and AMD Am29000 RISC lines. The another significant approach was to perceive a new architecture and to execute it from the very starting as a superscalar line. This happened when IBM announced its RS/6000 processor in 1990, later renamed the Power1.