RISC stands for Reduced Instruction Set Computer. In Reduced Instruction Set Computer (RISC) architecture, the instruction set of the computer is simplified to reduce the execution time. RISC has a small set of instructions, which generally include register-to-register operations.
Thus, data is stored in processor registers for computations, and results of the computations are transferred to the memory using store instructions. All operations are performed within the registers of the CPU. In RISC, all instructions have simple register addressing and hence use less number of addressing modes.
RISC uses relatively a simple instruction format and is easy to decode. Here, the instruction length can be fixed and aligned on word boundaries. The RISC processors can execute one instruction per clock cycle.
This is done using pipelining, which involves overlapping the fetch, decode, and execute phases of two or three instructions. As RISC takes relatively a large number of registers in the processor unit, it takes less time to execute its program when compared to CISC.
There are various features of CISC Processor that are as follows −