A bus transfer is the most effective method to send data by using a common bus system. It is constructed using common bus registers in multiple registers. The mechanism of the bus includes a collection of lines. These lines are registers of one bit each, which share only one information at a time. The data transfer is contained by the control signals.
The two methods that can be used in Bus transfer are as follows −
A common bus can be generated using a multiplexer. It facilitates in choosing the source register to place the binary data on the bus. The bus register has input and output gating controlled by control signals. The diagram demonstrates the input and output gating of registers.
The figure shows input and output gating. The switches are controlled by control signals. Rin and Rout are the input and output gating of the register Ri. When the signal is ON, Ri is set to 1 and when the signal is OFF, Ri is set to 0.
When the input gating Rin is set to 1, the data is loaded into the register bus Ri accessible on the common bus. When Rout is set to 1, the contents of the register Ri are placed on the data bus. It is referred to as input enabled and output enabled signals. The functions that take place inside the processor are in sync with the clock pulse.
Three-state buffers can generate a common bus. The buffer is an area of the memory, which is added in between the other devices to block several interactions and to connect the support. It is established on the three states, 1, 0, and the open circuit. These three states defines are as follows −
The diagram demonstrates the logic symbols and the associated truth table.
As shown in the figure −