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What are the elements of Bus Design in Computer Architecture?
There are few basic guidelines or design elements that distribute to categorize and differentiate buses.
Bus lines can be reported into two generic types are dedicated and multiplexed. A dedicated bus line is permanently authorized either to one function or a physical subgroup of computer components. A multiplexed bus line is assigned too many functions based on some parameters.
Method of Arbitration
In all but the simplest systems, more than one module can require control of the bus. Therefore only one unit at a time can strongly transfer over the bus, some method of arbitration is required. Various methods can be classified as centralized or distributed.
In a centralized scheme, a single hardware device defined as a bus controller or arbiter is important for assigning time on the bus. In a distributed scheme, there is no central controller. Each module includes access control logic and the modules help together to transfer the bus.
Timing defines how events are integrated on the bus. With synchronous timing, the circumstances of events on the bus are persistent by a clock. The figure shows the timing diagram for a synchronous read operation.
With asynchronous timing, the circumstances of one event on a bus follows and are based on the circumstances of a previous event. In this example, the CPU places address and read signals on the bus.
After pausing for these signals to maintain, it declares an MSYN (master sync) signal. It indicating the presence of valid current address and control signals. The memory module responds with data and an SSYN (slave sync) signal, indicating the response.
The width of the data has an impact on system execution. The wider the data bus, the higher the number of bits moved at one time. The width of the address bus has an impact on system capacity, that is, the wider the address bus, the higher the dimension of locations that can be referenced.
Data Transfer Type
A bus provides several data transfer types as shown in the figure. All buses provide both write (master to slave) and read (slave to master) assigns.
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