What are the methods of cache-coherency in computer architecture?

There are two methods of cache-coherency which are as follows −

  • Cache–Memory Coherence

In a single cache system, coherence between memory and the cache is maintained using one of two policies − (1) write-through, and (2) write-back. When a task running on a processor P requests the data in memory location X, for example, the contents of X are copied to the cache, where it is passed on to P.

When P updates the value of X in the cache, the other copy in memory also needs to be updated to maintain consistency. In write-through, the memory is updated every time the cache is updated, while in write-back, the memory is updated only when the block in the cache is being replaced. The table shows the write-through versus write-back policies.           

Write-Through vs. Write-Back

2P reads XXXXX
3P updates XXXXX
  • Cache–Cache Coherence

In a multiprocessing system, when a task running on processor P requests the data in global memory location X, for example, the contents of X are copied to processor P’s local cache, where it is passed on to P.

There are two fundamental cache coherence policies − (1) write-invalidate, and (2) write-update. Write-invalidate maintains consistency by reading from local caches until a write occurs.

When any processor updates the value of X through a write, posting a dirty bit for X invalidates all other copies. For example, processor Q invalidates all other copies of X when it writes a new value into its cache. This sets the dirty bit for X. Q can continue to change X without further notifications to other caches because Q has the only valid copy of X.

However, when processor P wants to read X, it must wait until X is updated and the dirty bit is cleared. Write-update maintains consistency by immediately updating all copies in all caches. All dirty bits are set during each writes operation. After all, copies have been updated, all dirty bits are cleared. The table shows the write-update versus write-invalidate policies.

Write-Update vs. Write-Invalidate

SerialEventP’s CacheQ’s CacheP’s CacheQ’s Cache
1P reads XX
2Q reads XXXXX
3Q updates XX’X’INVX’
4Q updates X’X’’X’’INVX’’