Found 826 Articles for Network

A scheduling system consists of program tasks, a target machine, and a schedule in which a specific performance criterion is optimized.Program Tasks − The characteristics of a parallel program can be defined as the system (T,

The general scheduling problem has been described in different ways in different fields. The classical problem of job sequencing in production management has influenced most of the solutions to this problem, which generally assumes a set of resources that could provide service to a set of consumers. The main objective is to find an efficient policy for managing the access to the resources by the consumers to optimize some desired performance measures.In distributed systems, the scheduling problem arises because the concurrent parts of a program or set of programs must be arranged in time and space so that the overall ... Read More

There are two methods of cache-coherency which are as follows −Cache–Memory CoherenceIn a single cache system, coherence between memory and the cache is maintained using one of two policies − (1) write-through, and (2) write-back. When a task running on a processor P requests the data in memory location X, for example, the contents of X are copied to the cache, where it is passed on to P.When P updates the value of X in the cache, the other copy in memory also needs to be updated to maintain consistency. In write-through, the memory is updated every time the cache ... Read More

A shared memory model is one in which processors connects by reading and writing locations in a shared memory that is similarly applicable by all processors. Each processor can have registers, buffers, caches, and local memory banks as more memory resources. Some basic issues in the design of shared-memory systems have to be taken into consideration. These involves access control, synchronization, protection, and security.Access control specifies which process accesses are achievable to which resources. Access control models create the needed check for each access request issued by the processors to the shared memory, against the contents of the access control ... Read More

The character-oriented protocol is depends the binary code of a character set. The code generally used is ASCII (American Standard Code for Information Interchange). It is a 7-bit code with an eighth bit used for parity. The code has 128 characters, of which 95 are graphic characters and 33 are control characters. The graphic characters involves the upper- and lowercase letters, the ten numerals, and multiple unique symbols.The control characters are used to route information, organizing the test in the desired structure, and for the design of the printed page. The characters that control the transmission are known as communication ... Read More

The Intel 8089 l/0 processor is contained in a 40-pin integrated circuit package. Within the 8089 are two independent units called channels. Each channel combines the general characteristics of a processor unit with those of a direct memory access controller.The 8089 is designed to function as an IOP in a microcomputer system where the Intel 8086 microprocessor is used as the CPU. The 8086 CPU initiates an l/0 operation by building a message in memory that describes the function to be performed. The 8089 IOP reads the message from memory, carries out the operation, and notifies the CPU when it ... Read More

The I/O processor in the IBM 370 computer is known as a channel. A general computer system configuration contains multiple channels with each channel connected to one or more I/O devices.There are three types of channels including a multiplexer, selector, and block-multiplexer. The multiplexer channel can be linked to multiple slow and medium-speed devices and is adequate for operating with several I/O devices together.The selector channel is created to manage one I/O operation at a time and is generally used to control one high-speed device. The block-multiplexer channel merges the features of both the multiplexer and selector channels. It supports ... Read More

The daisy-chaining method of creating priority includes a serial connection of all devices that request an interrupt. The device with the highest priority is located in the first position, followed by lower-priority devices up to the device with the lowest priority, which is situated last in the chain. This technique of connection between three devices and the CPU.The interrupt request line is average to all devices and design a wired logic connection. If some device has its interrupt signal in the low-level state, the interrupt line goes to the low-level state and enables the interrupt input in the CPU. When ... Read More

The block diagram of an asynchronous communication interface is displayed in the figure. It works as both a sender and a receiver. The interface is boot up for a specific mode of transfer using a control byte that is loaded into its control register. The transmitter register receives a data byte from the CPU by the data bus. This byte is sent to a shift register for serial transmission.The receiver portion receives serial information into another shift register, and when a finalize data byte is acquired, it is moved to the receiver register. The CPU can choose the receiver register ... Read More

The transfer of data between two units can be finished in parallel or serial. In parallel data transmission, each bit of the message has its direction, and the complete message is sent at a similar time. This defines that an n-bit message should be sent through n separate conductor paths.In serial data transmission, each bit in the message is transmitted in sequence one at a time. This approach needed the use of one pair of conductors or one conductor and common ground. Parallel transmission is quicker but needed multiple wires. It is used for short distances and where speed is ... Read More