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VLSI Design - VHDL Introduction
VHDL stands for very high-speed integrated circuit hardware description language. It is a programming language used to model a digital system by dataflow, behavioral and structural style of modeling. This language was first introduced in 1981 for the department of Defense (DoD) under the VHSIC program.
Describing a Design
In VHDL an entity is used to describe a hardware module. An entity can be described using,
- Entity declaration
- Package declaration
- Package body
Let’s see what are these?
It defines the names, input output signals and modes of a hardware module.
entity entity_name is Port declaration; end entity_name;
An entity declaration should start with ‘entity’ and end with ‘end’ keywords. The direction will be input, output or inout.
|In||Port can be read|
|Out||Port can be written|
|Inout||Port can be read and written|
|Buffer||Port can be read and written, it can have only one source.|
Architecture can be described using structural, dataflow, behavioral or mixed style.
architecture architecture_name of entity_name architecture_declarative_part; begin Statements; end architecture_name;
Here, we should specify the entity name for which we are writing the architecture body. The architecture statements should be inside the ‘begin’ and ‘énd’ keyword. Architecture declarative part may contain variables, constants, or component declaration.
Data Flow Modeling
In this modeling style, the flow of data through the entity is expressed using concurrent (parallel) signal. The concurrent statements in VHDL are WHEN and GENERATE.
Besides them, assignments using only operators (AND, NOT, +, *, sll, etc.) can also be used to construct code.
Finally, a special kind of assignment, called BLOCK, can also be employed in this kind of code.
In concurrent code, the following can be used −
- The WHEN statement (WHEN/ELSE or WITH/SELECT/WHEN);
- The GENERATE statement;
- The BLOCK statement
In this modeling style, the behavior of an entity as set of statements is executed sequentially in the specified order. Only statements placed inside a PROCESS, FUNCTION, or PROCEDURE are sequential.
PROCESSES, FUNCTIONS, and PROCEDURES are the only sections of code that are executed sequentially.
However, as a whole, any of these blocks is still concurrent with any other statements placed outside it.
One important aspect of behavior code is that it is not limited to sequential logic. Indeed, with it, we can build sequential circuits as well as combinational circuits.
The behavior statements are IF, WAIT, CASE, and LOOP. VARIABLES are also restricted and they are supposed to be used in sequential code only. VARIABLE can never be global, so its value cannot be passed out directly.
In this modeling, an entity is described as a set of interconnected components. A component instantiation statement is a concurrent statement. Therefore, the order of these statements is not important. The structural style of modeling describes only an interconnection of components (viewed as black boxes), without implying any behavior of the components themselves nor of the entity that they collectively represent.
In Structural modeling, architecture body is composed of two parts − the declarative part (before the keyword begin) and the statement part (after the keyword begin).
Logic Operation – AND GATE
VHDL Code: Library ieee; use ieee.std_logic_1164.all; entity and1 is port(x,y:in bit ; z:out bit); end and1; architecture virat of and1 is begin z<=x and y; end virat;
Logic Operation – OR Gate
VHDL Code: Library ieee; use ieee.std_logic_1164.all; entity or1 is port(x,y:in bit ; z:out bit); end or1; architecture virat of or1 is begin z<=x or y; end virat;
Logic Operation – NOT Gate
VHDL Code: Library ieee; use ieee.std_logic_1164.all; entity not1 is port(x:in bit ; y:out bit); end not1; architecture virat of not1 is begin y<=not x; end virat;
Logic Operation – NAND Gate
VHDL Code: Library ieee; use ieee.std_logic_1164.all; entity nand1 is port(a,b:in bit ; c:out bit); end nand1; architecture virat of nand1 is begin c<=a nand b; end virat;
Logic Operation – NOR Gate
VHDL Code: Library ieee; use ieee.std_logic_1164.all; entity nor1 is port(a,b:in bit ; c:out bit); end nor1; architecture virat of nor1 is begin c<=a nor b; end virat;
Logic Operation – XOR Gate
VHDL Code: Library ieee; use ieee.std_logic_1164.all; entity xor1 is port(a,b:in bit ; c:out bit); end xor1; architecture virat of xor1 is begin c<=a xor b; end virat;
Logic Operation – X-NOR Gate
VHDL Code: Library ieee; use ieee.std_logic_1164.all; entity xnor1 is port(a,b:in bit ; c:out bit); end xnor1; architecture virat of xnor1 is begin c<=not(a xor b); end virat;
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