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What is Horizontal Microcode?
In horizontal microcode, each micro-operation is represented by one bit in each microinstruction. Horizontal microcode is generally included in a fairly wide control save it is not exceptional for each work to be 56 bits or more. On each click of a sequencer clock, a microcode word is read, decoded, and used to control the functional components which create up the CPU. The micro-operations and their mnemonics are shown in the table.
Microoperations and their mnemonics for the very simple CPU
| Mnemonic | Micro-Operation |
|---|---|
| ARPC | AR←PC |
| ARDR | AR←DR[5….0] |
| PCIN | PC←PC+1 |
| PCDR | PC←DR[5…0] |
| DRM | DR←M |
| IRDR | IR←DR[7…6] |
| PLUS | AC←AC+DR |
| AND | AC←AC ^ DR |
| ACIN | AC←AC+1 |
Since there are nine micro-operations, each word of microcode requires 9 bits to represent them, 1 bit per micro-operation. A value of 1 means the micro-operation is to occur and a value of 0 means that it does not. To complete the microcode, it can simply fill in the values for the micro-operations. The resultant microcode is shown in the table.
Preliminary horizontal microcode for the very simple microsequencer
| State | Address | SEL | ARPC | ARDR | PCIN | PCDR | DRM | IRDR | PLUS | AND | ACIN | ADDR |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| FETCH1 | 0000 (0) | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0001 |
| FETCH2 | 0001(1) | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0010 |
| FETCH3 | 0010(2) | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | XXXX |
| ADD1 | 1000(8) | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1001 |
| ADD2 | 1001(9) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0000 |
| AND1 | 1010(10) | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1011 |
| AND2 | 1011(11) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0000 |
| JMP1 | 1100(12) | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0000 |
| INC1 | 1110(14) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0000 |
Before generating the control signals, it reviews the microcode to see how it can be optimized. ARDR and IRDR have the same value. It cannot require two outputs to represent the same value, it can use one output to derive both micro-operations, AIDR, which combines both microoperations AR←DR[5….0]and IR←DR[7…6]. The revised microcode is displayed in the table.
Optimized horizontal microcode for the very simple microsequencer
| State | Address | SEL | ARPC | ARDR | PCIN | PCDR | DRM | IRDR | PLUS | AND | ACIN | ADDR |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| FETCH1 | 0000 (0) | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0001 |
| FETCH2 | 0001(1) | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0010 |
| FETCH3 | 0010(2) | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | XXXX |
| ADD1 | 1000(8) | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1001 |
| ADD2 | 1001(9) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0000 |
| AND1 | 1010(10) | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1011 |
| AND2 | 1011(11) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0000 |
| JMP1 | 1100(12) | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0000 |
| INC1 | 1110(14) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0000 |
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