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What is Vertical Microcode?
In vertical microcode, each microinstruction is encoded i.e., the bit field can pass through intermediate combinatory logic which in turn creates the actual control signals for internal CPU components (ALU, registers, etc). In vertical microcode, the micro-operations are grouped into fields such that no more than one micro-operation in a field is active during any state. Then a unique field value is assigned to each micro-operation in the field.
For example, a field with eight different micro-operations would require 3 bits, each value from 000 to 111 would be assigned to one of the eight micro-operations. The micro-operation field bits are output from the microcode memory to a decoder. The output of the decoder is the micro-operations directly generated under horizontal microcode.
Whenever two micro-operations appear during a similar state, sign them to multiple fields. Each field can output the value of only one micro-operation during a cycle. If two micro-operations are to occur simultaneously, they cannot be in the same field.
It includes a NOP in each field if important. Likely, some states will not require that any micro-operations in a given field be active. As shown in the figure, some value must be output from the microcode memory, even when no micro-operation is active. It can be distributing the remaining micro-operations to create the finest use of the micro-operation field bits. The designer should try to make the best use of the field bits. For example, a field with five, six, seven, or eight micro-operations (including a NOP) requires 3 bits.
Group micro-operations that change the similar registers in the equal fields. Because two micro-operations cannot modify the same register simultaneously, it is possible to place them in the same micro-operation field.
Group micro-operations that change the similar registers in the equal fields. Because two micro-operations cannot modify the same register simultaneously, it is possible to place them in the same micro-operation field.
M1 M2 NOP NOP DRM PCIN
Because PCIN and PCDR both change PC, it can add PCDR to M2. Next, it can arbitrarily assign the remaining micro-operations to the fields, keeping micro-operations that alter the similar register in the equal field. There is one possible scenario that produces the following assignment.
M1 M2 NOP NOP DRM PCIN ACIN PCDR PLUS ARPC AND AIDR
Each field has five micro-operations, thus requiring 3 bits per field for a total of 6 bits. Bu juggling the assignments around can reduce the total number of bits. Simply moving AIDR from M2 to M1 changes the number of micro-operations in M1 and M2 from 5 and 5 to 6 and 4, respectively. M1 requires 3 bits, but M2 requires only 2 bits. Every word of microcode would be one bit less wide.
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