In 8085 Instruction set, SHLD is a mnemonic, which stands for Store HLpair using Direct addressing in memory location whose 16-bit address is denoted as a16. As HL pair has to be stored, so it has to be stored in two consecutive locations starting at the address a16. We know that H and L are 8-bit registers. So their contents will be stored in two consecutive memory locations as each memory location can hold 8-bits of data. This instruction uses absolute addressing mode for specifying the destination. It occupies 3-Bytes in the memory.
|Mnemonics, Operand||Opcode(in HEX)||Bytes|
Let us consider SHLD 4050H as a sample instruction of this type. It is a 3-Byte instruction so occupies 3 consecutive memory locations. Let us consider that H and L registers are containing BBH and AAH as initial contents. 4050H and 4051H memory locations are holding data CCH and DDH respectively. So after execution of the instruction SHLD 4050H, the contents of 4050H and 4051H memory locations would be AAH and BBH respectively. Here is the tracing table for better understanding.
|200B||22||SHLD 4050H||Store HL register pair’s content to memory locations 4050H and 4051H respectively.|
|200C||50||Low order Byte of the address|
|200D||40||High order Byte of the address|
Note that there are no instructions in 8085 like SBCD a16 and SDED a16. As HL pair is the most important register pair, whose contents can be stored in memory in more ways than any other register pair.
Let us consider the timing diagram of the instruction SHLD 4050H execution.
Summary − So this instruction SHLD 4050H requires 3-Bytes, 5-Machine Cycles (Opcode Fetch, Memory Read, Memory Read, Memory Write, Memory Write) and 16 T-States for execution as shown in the timing diagram.