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Instruction type XTHL in 8085 Microprocessor
In 8085 Instruction set, XTHL is a mnemonic that stands for “eXchange Top of stack with HL”. This instruction exchanges the contents of the top two locations of the stack with the contents of register pair HL.
Here it is not an exchange between SP with HL.It occupies only 1-Byte in memory.
| Mnemonics, Operand | Opcode(in HEX) | Bytes |
|---|---|---|
| XTHL | E3 | 1 |
The result of execution of this instruction XTHL is shown below with a sample instruction and along with tracing table. Let us consider HL and SP are having contents BBAAH and 4050H. And at locations 4050H and at 4051H the memory contents are CCH and DDH respectively. After execution of instruction XTHL the updated contents of 4050H and 4051H would be AAH and BBH respectively. And H and L registers will contain DDH and CCH respectively. So here is the tracing table −
| Before | After | |
|---|---|---|
(HL) |
BBAAH | DDCCH |
(SP) |
4050H | 4050H |
(4050H) |
CCH | AAH |
(4051H) |
DDH | BBH |
| Address | Hex Codes | Mnemonic | Comment |
|---|---|---|---|
| 200E | E3 | XTHL | At Location (SP) ← Content of L register At Location (SP + 1) ← Content of H register |
The timing diagram against this instruction XTHL execution is as follows −
Summary − So this instruction XTHL requires 1-Byte, 5-Machine Cycles (Opcode Fetch, Memory Read, Memory Read, Memory Write, Memory Write) and 16 T-States for execution as shown in the timing diagram.
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