Embedded Systems - SFR Registers


A Special Function Register (or Special Purpose Register, or simply Special Register) is a register within a microprocessor that controls or monitors the various functions of a microprocessor. As the special registers are closely tied to some special function or status of the processor, they might not be directly writable by normal instructions (like add, move, etc.). Instead, some special registers in some processor architectures require special instructions to modify them.

In the 8051, register A, B, DPTR, and PSW are a part of the group of registers commonly referred to as SFR (special function registers). An SFR can be accessed by its name or by its address.

The following table shows a list of SFRs and their addresses.

Byte Address Bit Address
F0 F7 F6 F5 F4 F3 F2 F1 F0 B
E0 E7 E6 E5 E4 E3 E2 E1 E0 ACC
D0 D7 D6 D5 D4 D3 D2 - D0 PSW
B8 - - - BC BB BA B9 B8 IP
B0 B7 B6 B5 B4 B3 B2 B1 B0 P3
A2 AF - - AC AB AA A9 A8 IE
A0 A7 A6 A5 A4 A3 A2 A1 A0 P2
99 Not bit Addressable SBUF
98 9F 9E 9D 9C 9B 9A 99 98 SCON
90 97 96 95 94 93 92 91 90 P1
8D Not bit Addressable TH1
8C Not bit Addressable TH0
8B Not bit Addressable TL1
8A Not bit Addressable TL0
89 Not bit Addressable TMOD
88 8F 8E 8D 8C 8B 8A 89 88 TCON
87 Not bit Addressable PCON
83 Not bit Addressable DPH
82 Not bit Addressable DPL
81 Not bit Addressable SP
80 87 87 85 84 83 82 81 80 P0

Consider the following two points about the SFR addresses.

  • A special function register can have an address between 80H to FFH. These addresses are above 80H, as the addresses from 00 to 7FH are the addresses of RAM memory inside the 8051.

  • Not all the address space of 80 to FF are used by the SFR. Unused locations, 80H to FFH, are reserved and must not be used by the 8051 programmer.

CY PSW.7 Carry Flag
AC PSW.6 Auxiliary Carry Flag
F0 PSW.5 Flag 0 available to user for general purpose.
RS1 PSW.4 Register Bank selector bit 1
RS0 PSW.3 Register Bank selector bit 0
OV PSW.2 Overflow Flag
- PSW.1 User definable FLAG
P PSW.0 Parity FLAG. Set/ cleared by hardware during instruction cycle to indicate even/odd number of 1 bit in accumulator.

In the following example, the SFR registers’ names are replaced with their addresses.


We can select the corresponding Register Bank bit using RS0 and RS1 bits.

RS1 RS2 Register Bank Address
0 0 0 00H-07H
0 1 1 08H-0FH
1 0 2 10H-17H
1 1 3 18H-1FH

The Program Status Word (PSW) contains status bits to reflect the current state of the CPU. The 8051 variants provide one special function register, PSW, with this status information. The 8251 provides two additional status flags, Z and N, which are available in a second special function register called PSW1.