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Embedded Systems - SFR Registers
A Special Function Register (or Special Purpose Register, or simply Special Register) is a register within a microprocessor that controls or monitors the various functions of a microprocessor. As the special registers are closely tied to some special function or status of the processor, they might not be directly writable by normal instructions (like add, move, etc.). Instead, some special registers in some processor architectures require special instructions to modify them.
In the 8051, register A, B, DPTR, and PSW are a part of the group of registers commonly referred to as SFR (special function registers). An SFR can be accessed by its name or by its address.
The following table shows a list of SFRs and their addresses.
|Byte Address||Bit Address|
|99||Not bit Addressable||SBUF|
|8D||Not bit Addressable||TH1|
|8C||Not bit Addressable||TH0|
|8B||Not bit Addressable||TL1|
|8A||Not bit Addressable||TL0|
|89||Not bit Addressable||TMOD|
|87||Not bit Addressable||PCON|
|83||Not bit Addressable||DPH|
|82||Not bit Addressable||DPL|
|81||Not bit Addressable||SP|
Consider the following two points about the SFR addresses.
A special function register can have an address between 80H to FFH. These addresses are above 80H, as the addresses from 00 to 7FH are the addresses of RAM memory inside the 8051.
Not all the address space of 80 to FF are used by the SFR. Unused locations, 80H to FFH, are reserved and must not be used by the 8051 programmer.
|AC||PSW.6||Auxiliary Carry Flag|
|F0||PSW.5||Flag 0 available to user for general purpose.|
|RS1||PSW.4||Register Bank selector bit 1|
|RS0||PSW.3||Register Bank selector bit 0|
|-||PSW.1||User definable FLAG|
|P||PSW.0||Parity FLAG. Set/ cleared by hardware during instruction cycle to indicate even/odd number of 1 bit in accumulator.|
In the following example, the SFR registers’ names are replaced with their addresses.
We can select the corresponding Register Bank bit using RS0 and RS1 bits.
The Program Status Word (PSW) contains status bits to reflect the current state of the CPU. The 8051 variants provide one special function register, PSW, with this status information. The 8251 provides two additional status flags, Z and N, which are available in a second special function register called PSW1.