Found 312 Articles for Computer Architecture

An instruction pipeline reads consecutive instructions from memory while in the other segments the previous instructions are being implemented. Pipeline processing appears both in the data flow and in the instruction stream. This leads to the overlapping of the fetch and executes the instruction and hence simultaneous operations are performed.There is one possible more event associated with such a design is that instruction can generate a branch out of a sequence. In this method, the pipeline is clear and all the instructions that have previously been read from memory after the branch instruction should be rejected.A computer can be constructed ... Read More

Pipeline arithmetic units are generally discovered in very large-speed computers. It can execute floating-point operations, multiplication of fixed-point numbers, and the same computations encountered in mathematical problems.The inputs to the floating-point adder pipeline are two normalized floating-point binary numbers represented as −X = A x 2aY = B x 2bWhere A and B are two fractions that define the mantissa and a and b are the exponents. The floating-point addition and subtraction can be implemented in four segments, as a displayed figure. The registers labeled R is located between the segments to save intermediate outcomes. The suboperations that are implemented ... Read More

Pipelining is a technique of breaking a sequential process into small fragments or sub-operations. The execution of each of these sub-procedure takes place in a certain dedicated segment that functions together with all other segments. There are three types of Pipelining conflicts that are as follows −Resource ConflictsThese conflicts arise due to insufficient resources wherein it is not possible to overlap the operations. The performance of pipelined processor depends on either of the two conditions are as follows −Whether or not the functional units are pipelined?Do the multiple execution units allow all available mixture of instructions in the pipeline?If for ... Read More

Pipelining defines a technique of decomposing a sequential process into sub-operations, with each sub-operation being implemented in an enthusiastic segment that works together with all other segments. There are the following techniques that can be followed to avoid pipelining conflicts −Hardware Interlocks − Hardware interlocks are electronic circuits that detect instructions whose source operands are destinations of instructions further up in the pipeline. After detecting this situation, the instruction whose source is not available is delayed by a suitable number of clock periods. In this way, the conflict is resolved.Operand Forwarding − This procedure need special hardware to identify a ... Read More

Pipelining is a technique of breaking a sequential process into small fragments or sub-operations. The execution of each of these sub-procedure takes place in a certain dedicated segment that functions together with all other segments. The pipeline has a collection of processing segments which helps the flow of binary information.The internal working in a pipeline is such that the outcome of one segment is conveyed to the next segment in the pipeline until the desired result is obtained. The outcome is acquired after the information is developed through all segments.The term “pipeline” indicates that the flow of information takes place ... Read More

Parallel processing is an approach that can denote a huge class of methods that can give simultaneous data-processing functions to improve the computational speed of a computer system.Rather than processing each instruction sequentially as in a traditional computer, a parallel processing system can implement concurrent data processing to manage quicker implementation time.For example, while an instruction is being implemented in the ALU, the next instruction can be read from memory. The system can have multiple ALUs and can implement various instructions at a similar time.The system can have multiple processors operating together. Parallel processing aims to speed up the computer ... Read More

The hypercube interconnection is also defined as a binary n-cube multiprocessor. The hypercube is treated to be a loosely coupled system. This system is composed of N = 2n processors that are linked in an n-dimensional binary cube. Each processor denotes a node of the cube.Each processor includes a direct communication route to n other neighbour processors. These routes are associated with the edges of the cube. The processors can be authorized with 2n distinct n-bit binary addresses. Each processor send differs from that of each of its n neighbors by directly one-bit position.The figure displayed the hypercube structure for ... Read More

Omega switching network is one such topology that is shown in the figure. In this configuration, there is directly one direction from each source to any specific destination.There is some request design, however, cannot be linked together. For example, any two sources cannot be linked together to destinations 000 and 001.As shown in the figure, a specific request is started in the switching network through the source that sends a 3-bit pattern depicting the destination number.Each level checks a multiple bit to specify the 2 x 2 switch setting as the binary design transfer through the network. Level 1 determines ... Read More

The basic element of a multistage network is a two-input, two-output interchange switch. As displayed in the figure, the 2 X 2 switch has two inputs labeled A and B, and two outputs labeled 0 and 1.There are control signals related to the switch. The control signals start interconnection between the input and output terminals. The switch can join input A to either of the outputs. Terminal B of the switch facilitates similarly. The switch can also arbitrate between conflicting requests.In case, inputs A and B request the same output terminals, it is possible that only one of the inputs ... Read More

The crossbar switch organization includes various crosspoints that are located at intersections between processor buses and memory module directions. The diagram shows a crossbar switch interconnection between four CPUs and four memory modules.The tiny square in each crosspoint is a switch that decides the direction from a processor to a memory module. Every switch point has to control logic to set up the transmission direction between a processor and memory.It determines the address that is located in the bus to decide whether its specific module is being addressed. It can also resolve several requests for an approach to the equal ... Read More