What are the techniques to avoid Pipelining Conflicts?

Computer ArchitectureComputer ScienceNetwork

Pipelining defines a technique of decomposing a sequential process into sub-operations, with each sub-operation being implemented in an enthusiastic segment that works together with all other segments. There are the following techniques that can be followed to avoid pipelining conflicts −

  • Hardware Interlocks − Hardware interlocks are electronic circuits that detect instructions whose source operands are destinations of instructions further up in the pipeline. After detecting this situation, the instruction whose source is not available is delayed by a suitable number of clock periods. In this way, the conflict is resolved.
  • Operand Forwarding − This procedure need special hardware to identify a conflict and then prevent it by routing the information through a unique direction between pipeline segments. This approach needed additional hardware direction through MUXs (multiplexers).
  • Delayed Branching − In this procedure, the compiler is responsible for resolving the pipelining conflicts. The compiler identifies the branch instructions and arranges the machine language code sequence by adding appropriate instructions that hold the pipeline functioning without obstructions.
  • Branch Prediction − This method utilizes some sort of intelligent forecasting through appropriate logic. A pipeline with branch prediction guesses the result of a conditional branch instruction before it is implemented. The pipeline fetches the stream of instructions from a predicted path, thus saving the time that is wasted by branch penalties.
  • Speculative Execution − The advantage of branch prediction is that it helps the instructions following the branch to be fetched and executed without any delay. However, this should be completed on a speculative basis.

Speculative execution defines that instructions are implemented before the processor is certain that they are on the right implementation path. Therefore, care should be taken that no processor registers or memory locations are refreshed just before it is accepted that these instructions have to be performed.

If the branch decision denotes alternatively, the instructions and all their related data in the implementation units should be removed and the correct instructions should be fetched and executed.

raja
Published on 27-Jul-2021 14:52:06
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