The crossbar switch organization includes various crosspoints that are located at intersections between processor buses and memory module directions. The diagram shows a crossbar switch interconnection between four CPUs and four memory modules.
The tiny square in each crosspoint is a switch that decides the direction from a processor to a memory module. Every switch point has to control logic to set up the transmission direction between a processor and memory.
It determines the address that is located in the bus to decide whether its specific module is being addressed. It can also resolve several requests for an approach to the equal memory module on a fixed priority basis.
The diagram shows the functional design of a crossbar switch linked to one memory module. The circuit includes multiplexers that choose the information, address, and control from one CPU for interaction with the memory module.
Priority levels are created by the arbitration logic to choose one CPU when multiple CPUs try to access the equal memory. The multiplexers are regulated with the binary code that is created through a priority encoder inside the arbitration logic.