Computer Science Articles - Page 25 of 62

The character-oriented protocol is depends the binary code of a character set. The code generally used is ASCII (American Standard Code for Information Interchange). It is a 7-bit code with an eighth bit used for parity. The code has 128 characters, of which 95 are graphic characters and 33 are control characters. The graphic characters involves the upper- and lowercase letters, the ten numerals, and multiple unique symbols.The control characters are used to route information, organizing the test in the desired structure, and for the design of the printed page. The characters that control the transmission are known as communication ... Read More

The Intel 8089 l/0 processor is contained in a 40-pin integrated circuit package. Within the 8089 are two independent units called channels. Each channel combines the general characteristics of a processor unit with those of a direct memory access controller.The 8089 is designed to function as an IOP in a microcomputer system where the Intel 8086 microprocessor is used as the CPU. The 8086 CPU initiates an l/0 operation by building a message in memory that describes the function to be performed. The 8089 IOP reads the message from memory, carries out the operation, and notifies the CPU when it ... Read More

The I/O processor in the IBM 370 computer is known as a channel. A general computer system configuration contains multiple channels with each channel connected to one or more I/O devices.There are three types of channels including a multiplexer, selector, and block-multiplexer. The multiplexer channel can be linked to multiple slow and medium-speed devices and is adequate for operating with several I/O devices together.The selector channel is created to manage one I/O operation at a time and is generally used to control one high-speed device. The block-multiplexer channel merges the features of both the multiplexer and selector channels. It supports ... Read More

The daisy-chaining method of creating priority includes a serial connection of all devices that request an interrupt. The device with the highest priority is located in the first position, followed by lower-priority devices up to the device with the lowest priority, which is situated last in the chain. This technique of connection between three devices and the CPU.The interrupt request line is average to all devices and design a wired logic connection. If some device has its interrupt signal in the low-level state, the interrupt line goes to the low-level state and enables the interrupt input in the CPU. When ... Read More

The block diagram of an asynchronous communication interface is displayed in the figure. It works as both a sender and a receiver. The interface is boot up for a specific mode of transfer using a control byte that is loaded into its control register. The transmitter register receives a data byte from the CPU by the data bus. This byte is sent to a shift register for serial transmission.The receiver portion receives serial information into another shift register, and when a finalize data byte is acquired, it is moved to the receiver register. The CPU can choose the receiver register ... Read More

The transfer of data between two units can be finished in parallel or serial. In parallel data transmission, each bit of the message has its direction, and the complete message is sent at a similar time. This defines that an n-bit message should be sent through n separate conductor paths.In serial data transmission, each bit in the message is transmitted in sequence one at a time. This approach needed the use of one pair of conductors or one conductor and common ground. Parallel transmission is quicker but needed multiple wires. It is used for short distances and where speed is ... Read More

Handshaking is an I/O control approach to synchronize I/O devices with the microprocessor. As several I/O devices accept or release data at a much lower cost than the microprocessor, this technique is used to control the microprocessor to operate with an I/O device at the I/O devices data transfer rate.The drawback of the strobe approach is that the source unit that starts the transfer has no method of knowing whether the destination unit has received the data element that was located in the bus. A destination unit that initiates the transfer has no method of knowing whether the source unit ... Read More

The strobe control technique of asynchronous data transfer operates a single control line to time each transfer. The strobe can be activated by either the source or the destination unit. The diagram shows a source-initiated transfer.The data bus gives the binary data from the source unit to the destination unit. Generally, the bus has multiple lines to transfer a unified byte or word. The strobe is a single line that instructs the destination unit when an accurate data word is accessible in the bus.As displayed in the timing diagram of figure (b), the source unit first places the data on ... Read More

In this transmission, signals are sent between the computers and external systems or vice versa asynchronously. This generally defines data that is sent at infrequent intervals instead of in a steady stream, which represents that the first element of the execute file might not ever be the first to be transmitted and enter at the destination.There are different elements of the execute data that are sent in multiple intervals, frequently together, but follow several paths approaching the destination. The transfer of asynchronous data doesn’t need the coordination or timing of bits between the two endpoints.The internal operations in a digital ... Read More

Isolated I/OIn the isolated I/O configurations, the CPU has definite input and output instructions, and each of these instructions is related to the address of an interface register. When the CPU fetches and decodes the operation code of an input or output instruction, it locates the address related to the instruction into the common address lines.Simultaneously, it enables the I/O read (for input) or I/O write (for output) control line. This instructs the external elements that are connected to the common bus that the address in the address lines is for an interface register and not for a memory word.In ... Read More