In 8085 Instruction set, RSTn is actually standing for “Restart n”. And in this case, n has a value from 0 to 7 only. Thus the eight possible RST instructions are there, e.g. RST 0, RST 1, …, RST 7. They are 1-Byte call instructions. Functionally RST n instruction is similar with:
RST n = CALL n*8
For example, let us consider RST 4 is functionally equivalent to CALL 4*8, i.e. CALL 32 = CALL 0020H. The advantage of RST 2 is that it is only 1 Byte, whereas CALL 0010H is 3-Byte long. Thus RST instructions are useful for branching to frequently used subroutines.
|Mnemonics, Operand||Opcode(in HEX)||In Binary||Bytes||Target Address (n*8)|
|RST 0||C7||1100 0111||1||0000H|
|RST 1||CF||1100 1111||1||0008H|
|RST 2||D7||1101 0111||1||0010H|
|RST 3||DF||1101 1111||1||0018H|
|RST 4||E7||1110 0111||1||0020H|
|RST 5||EF||1110 1111||1||0028H|
|RST 6||F7||1111 0111||1||0030H|
|RST 7||FF||1111 1111||1||0038H|
In the above table, it has been shown that if we analyze the RSTn Hex Codes than we are finding that middle most 3-bits are denoting the value for n (As highlighted in the table). And the other5 bits in the Byte provide the code for RST.
Let us consider, RST 4 is an example instruction of this type. It is a 1-Byte instruction. It is functionally same as CALL 0020H = PUSH PC + JMP 0010H. It causes a branch to subroutine starting from memory address 0020H. Similarly, RST 5 causes a branch to a subroutine at 5*8 = 0028H. Thus, the subroutine, which starts at location 0020H should not go beyond memory location 0027H. So at the most only eight locations are available for the subroutine, which is too small in general to keep the sub-routine bodies. This limitation is overcome by branching to a subroutine at some other memory location, like 4050H. It is achieved by the combination of RST 4 instruction, and JMP 4050H instruction at memory location 0020H, as shown in the following Fig.
The way in which the stack contents get affected due to the execution of RST 4 is shown below.
The way in which the stack contents get affected due to an execution of RST 4 is shown below.
In the Fig. the main program is starting from address 2000H with instruction LXI SP, 5000H to initialize SP with that memory address. The main program is having the terminating instruction HLT at address 2050H. In the main program at address 2020H the instruction is RST 4. So the computed target address will be 4*8 = 32 = 0020H. So the return address 2021H will be pushed at the top of the stack. So 20H will be pushed at stack location 4FFFH and 21H at address 4FFEH. So the updated SP address will be 4FFEH. And the control will be transferred to the address 0020H. At that address, we are having instruction JMP 4050H. So the program control will branch to that address 4050H. This subroutine is having the last instruction at address 4080H with the instruction RET. So return 2-Byte address will be popped out from the top of the stack. So the16-bit return address will be 2021H and SP will get initialized with 5000H again. So the main program will resume its execution and will terminate at 4080H address with instruction HLT as usual.
The timing diagram against this instruction RST 4 execution is as follows –
Summary − So this instruction RST 4 requires 1-Byte, 3-Machine Cycles (Opcode Fetch, Memory Write, Memory Write) and 12 T-States for execution as shown in the timing diagram.