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Registers B, C, D, E, H, and L in 8085 Microprocessor
Registers B, C, D, E, H, and L are general purpose registers in 8085 Microprocessor. All these GPRS are 8-bits wide. They are less important than the accumulator. They are used to store data temporarily during the execution of the program. For example, there is no instruction to add the contents of Band E registers. At least one of the operands has to be in A. Thus to add Band E registers, and to store the result in B register, the following have to be done.
Move to A register the contents of B register.
Then add A and E registers. The result will be in A.
Move this result from A register to B register.
It is possible to use these registers as pairs to store 16-bit information. Only BC, DE, and HLcan form register pairs. When they are used as register pairs in an instruction, the left register is understood to have the MS byte and the right register the LS byte. For example, in DEregister pair, the content of the D register is treated as the MS byte, and the content of E register is treated as the LS byte.
In the following figure depicts the architecture of 8085 microprocessor and with its register organization –
As an example to demonstrate how these registers can be used in our 8085assembly language programming, we are considering the following example. MVI is a mnemonic, which actually means “Move Immediate”.With this instruction, we can load a register with an 8-bits or1-Byte value. This instruction supports immediate addressing mode for specifying the data in the instruction. In the instruction “d8” stands for any 8-bit data, and ‘r’ stands for any one of the registers e.g. A, B, C, D, E, H or L. So this r can replace any one of the seven registers.
As ‘r’ can have any of the seven register names, so there are seven opcodes for this type of instruction. It occupies 2-Bytes in the memory.
| Mnemonics, Operand | Opcode | Bytes |
|---|---|---|
| MVI A, Data | 3E | 2 |
| MVI B, Data | 06 | 2 |
| MVI C, Data | 0E | 2 |
| MVI D, Data | 16 | 2 |
| MVI E, Data | 1E | 2 |
| MVI H, Data | 26 | 2 |
| MVI L, Data | 2E | 2 |
As the example, if we consider instruction MVI E, ABH then it means that ABH will be moved or copied to the register E. And as a result, the previous value of E will get overwritten.
| Address | HexCodes | Mnemonic | Comment |
|---|---|---|---|
| 2000 | 1E | MVI E, ABH | E ← ABH |
| 2001 | AB | ABH as operand |
This instruction will have seven T-states as shown below.
Summary − So this instruction MVI E, ABH requires 2-Bytes, 2-Machine Cycles (Opcode Fetch and Memory Read) and 7T-States for execution as shown in the timing diagram.
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