Intel 8255A - Pin Description


Let us first take a look at the pin diagram of Intel 8255A −

8255A Pin Diagram

Now let us discuss the functional description of the pins in 8255A.

Data Bus Buffer

It is a tri-state 8-bit buffer, which is used to interface the microprocessor to the system data bus. Data is transmitted or received by the buffer as per the instructions by the CPU. Control words and status information is also transferred using this bus.

Read/Write Control Logic

This block is responsible for controlling the internal/external transfer of data/control/status word. It accepts the input from the CPU address and control buses, and in turn issues command to both the control groups.


It stands for Chip Select. A LOW on this input selects the chip and enables the communication between the 8255A and the CPU. It is connected to the decoded address, and A0 & A1 are connected to the microprocessor address lines.

Their result depends on the following conditions −

CS A1 A0 Result
0 0 0 PORT A
0 0 1 PORT B
0 1 0 PORT C
0 1 1 Control Register
1 X X No Selection


It stands for write. This control signal enables the write operation. When this signal goes low, the microprocessor writes into a selected I/O port or control register.


This is an active high signal. It clears the control register and sets all ports in the input mode.


It stands for Read. This control signal enables the Read operation. When the signal is low, the microprocessor reads the data from the selected I/O port of the 8255.

A0 and A1

These input signals work with RD, WR, and one of the control signal. Following is the table showing their various signals with their result.

A1 A0 RD WR CS Result
0 0 0 1 0

Input Operation

PORT A → Data Bus
0 1 0 1 0 PORT B → Data Bus
1 0 0 1 0 PORT C → Data Bus
0 0 1 0 0

Output Operation

Data Bus → PORT A
0 1 1 0 0 Data Bus → PORT A
1 0 1 0 0 Data Bus → PORT B
1 1 1 0 0 Data Bus → PORT D